#12885: XHCI page fault under skylake
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Reporter: kallisti5 | Owner: nobody
Type: bug | Status: assigned
Priority: normal | Milestone: Unscheduled
Component: Drivers/USB/XHCI | Version: R1/Development
Resolution: | Keywords: skylake
Blocked By: | Blocking:
Has a Patch: 0 | Platform: All
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Comment (by kallisti5):
Intel xHCI, page 464:
{{{
The PCI Configuration space BAR0 and BAR1 fields contain a 64 bit address
that points to the base of the xHC PF0 MMIO space. This po inter will be
referred to as PBAR0.
}}}
I see the ohci driver doing this:
{{{
uint32 offset = sPCIModule->read_pci_config(fPCIInfo->bus,
fPCIInfo->device, fPCIInfo->function, PCI_base_registers, 4);
}}}
Does that somehow factor in the BAR0 vs BAR1 for 64-bit addresses?
_PCI::_GetBarInfo used by PCI_base_registers seems to do a little extra
math around 64-bit.
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Ticket URL: <https://dev.haiku-os.org/ticket/12885#comment:22>
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