All,
Brief Alterative Proposal Summary as it is evolving (shortcut names for
clarity)
Note, [Pin], [Pin Mapping], [Bus Label] and [Die Supply Pads] information
may be needed rail for connections to I/O buffer rails.
[Pad Pin Group] (could be [Package Group])
Replaces all existing IBIS Package Model formats with broad-band
electrical models
No Set includes Interconnect Models with terminals at the Buffer boundary
Simulations based on I/O pin_name selection(s)
PDN interface: Pin boundary, but connections to I/O supplies are
translated at the Pad boundary into bus_labels
Requires [Pin Mapping] because no direct mapping of rails to buffer supply
terminals is documented
Without PDN, internal [* Reference] rails are used, and [Pin Mapping]
optional
[Buffer Pad Group] (could be [On Die Group]
Adds electrical models to the on-die interconnect, but stops at the Pad
boundary
No Set includes Interconnect Models at the Pin boundary
No existing IBIS Package Model formats used, but EDA tool can optionally
use shorts to Pin boundary
Simulations based on I/O pin_name selection(s)
PDN interface: Pad boundary
Uses [Pin Mapping] rail to buffer supply terminal connections, OR uses
direct connections to buffer rail terminals
Without PDN, internal [* Reference] rails are used, and [Pin Mapping]
optional
[Full Path Group] (could be [Buffer Pin Group] or some other name)
Replaces all existing IBIS Package Model formats with broad-band
electrical models
Supports broadband Buffer to Pin connections where broad-band electrical
models exist between
Buffer-to-Pin, AND/OR between connected
Buffer-Pad, and Pad-Pin
Full path connections required for all I/Os and PDNs, if included
Simulations based on I/O pin_name selection(s)
PDN interface: Pin boundary
Uses [Pin Mapping] rail to buffer supply terminal connections, OR uses
direct connections to buffer rail terminals
Without PDN, internal [* Reference] rails are used, and [Pin Mapping]
optional
Added, for identification, but not part of earlier proposal
[PDN Group]
Full path PDN structure only
No I/O terminals in any Sets
Does not support broad-band I/O simulation within IBIS
Simulations based on I/O pin_name selection(s) and existing IBIS Package
Models that do not include PDN paths
I/O pins used as stimuli
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Main Points of Proposal Summary Here
- Group keywords tell EDA tool and model-maker purpose and intent;
and User can make informed selection
- Boundaries avoid default shorts or else allows rules for default
shorts for all paths to new boundary
- Except for PDN group, no mixing of existing IBIS Package models
(that would be contrary to broad-band simulation)
- Full Path connections likely to contain Sets for Interconnect
Model that have paths same boundaries
o Missing Sets likely to be an Error of omission or in linkages - must be
reported
o Unintended shorts may reduce quality of the Interconnect Structure
simulation
--
Bob Ross
Teraspeed Labs
www.teraspeedlabs.com <http://www.teraspeedlabs.com/>
bob@xxxxxxxxxxxxxxxxx
Direct: 503-246-8048
Office: 971-279-5325
