All,
The take-away from Bob' presentation is that one can define, and there
exists components that the reference node for device under test is not
available as a pin of the device. What was also determined is that EDA
tools can simulate a device in action, and measure the voltage of the I/O
terminal and all rail terminals of the device relative to any rail
terminal and shift those voltages to the DUT rail voltage conditions to
compare the voltage at the I/O terminal to the various threshold voltages
defined in the IBIS model any way the EDA tool chooses.
Choosing the rail terminal of a model or another POWER or GND pin of the
device is a useful concept, but is only meaningful with additional rules
on how to adjust the measurement thresholds when the DIA rails voltage are
not the same as the DUT rail voltages (scaling). IBIS only addresses
scaling for some specific DDR rules ([Receiver Thresholds]).
What we have re-enforced is the interpretation of GND, the earth ground
symbol and "absolute ground" in the IBIS spec as referring only to DUT
test conditions, and it is the responsibility of the EDA tool to adjust
simulation measurements at the I/O of the buffer and connections of C_comp
to be reference to an appropriate rail voltage at the buffer or rail
voltage at the pin.
Since the model maker (IC/Package Vendor) knows what is going on, then the
package models that connect the die to the PCB can reference the
appropriate signal name (VSS, VCC, VEE, GND, VSSQ, .) based on their
knowledge of each I/O buffer.
For C_comp, the model maker can guide the EDA tool by choosing a rail
signal_name as the [Pin Reference] for each model, otherwise the model
maker will rely on each EDA tools method to connect C_comp to a rail which
is 0.0V when DUT, or a GND signal name, or some other method the EDA
chooses.
Walter
Walter Katz
<mailto:wkatz@xxxxxxxxxx> wkatz@xxxxxxxxxx
Phone 303.449-2308
Mobile 303.335-6156
