Scott,
I am actually surprised that you are asking this question. Is
this a “loaded” question with some “punch line” coming after a
few attempts to answer it?
I may not know about all possible reasons, but in my mind, the
on-die interconnect is something that is located between the
buffer’s output stage transistors and the pad/bump on the die
where the die is connected to the package (or the outside world).
Making a model for this could include a description of the
pad/bump itself and the metal that goes between that place and
the output transistor of the buffer.
I am not sure whether an interposer would be part of this, since
we are talking about “on-die” interconnect now, but some of this
might be up to the model maker, how they decide to model the
various parts that need to be modeled.
But a power distribution network on the die, for example, could
definitely be part of this on-die interconnect model…
Thanks,
Arpad
==================================================================
From: Scott McMorrow [mailto:Scott@xxxxxxxxxxxxx]
Sent: Tuesday, March 14, 2017 12:28 PM
To: Muranyi, Arpad <Arpad_Muranyi@xxxxxxxxxx>; ibis-macro@xxxxxxxxxxxxx
Subject: RE: [ibis-macro] Re: Comments on BIRD158
On-die interconnect?
When this is referenced, what does it mean?
1) Interconnect physically on the active substrate?
2) Silicon, Glass, or other interposer between the substrate and the
package?
3) The redistribution layer?
4) All of the above?
Scott McMorrow, CTO Signal Integrity Group
Samtec
Office 401-284-1827 | +1-800-726-8329
www.samtec.com<http://www.samtec.com/>
