All, I added [End ?], and also indented to reflect hierarchy in both existing and proposed implementation. I added derating to the single ended model Walter Existing implementation ----------------------- [Component] MT47H256M4HQ [Manufacturer] Micron Technology,Inc. [Pin] signal_name model_name R_pin L_pin C_pin E8 CK CLKIN 41.35m 1.55nH 0.13pF F8 CK# CLKIN 42.93m 1.55nH 0.12pF [End Pin] | [Diff_pin] inv_pin vdiff tdelay_typ tdelay_min tdelay_max E8 F8 .250V 0ns NA NA [End Diff_pin] | [End Component] | [Model Selector] CLKIN CLKIN_533 Clock Input Model for 400/533 Speed Grade CLKIN_667 Clock Input Model for 667 Speed Grade CLKIN_1066 Clock Input Model for 800/1066 Speed Grade [End Model Selector] | [Model] CLKIN_533 Model_type Input ? [Receiver Thresholds] Vcross_low = 0.675V Vcross_high = 1.125V Vdiff_ac = 500mV Vdiff_dc = 250mV Tdiffslew_ac = 5.000ns ? [End Model] [End] (Note: ? represents the normal pseudo differential IBIS stuff) Proposed implementation ----------------------- [Component] MT47H256M4HQ [Manufacturer] Micron Technology,Inc. [Pin] signal_name model_name R_pin L_pin C_pin E8 CK CLKIN 41.35m 1.55nH 0.13pF F8 CK# CLKIN 42.93m 1.55nH 0.12pF [End Pin] | [Diff_pin_model] E8 F8 CLKIN_DIFF [End Diff_pin] | [End Component] | [Model Selector] CLKIN CLKIN_533 Singled Ended Clock Input Model for 400/533 Speed Grade CLKIN_667 Singled Ended Clock Input Model for 667 Speed Grade CLKIN_1066 Singled Ended Clock Input Model for 800/1066 Speed Grade [End Model Selector] | [Model Selector] CLKIN_DIFF CLKIN_DIFF_533 Differential Clock Input Model for 400/533 Speed Grade CLKIN_DIFF_667 Differential Clock Input Model for 667 Speed Grade CLKIN_DIFF_1066 Differential Clock Input Model for 800/1066 Speed Grade [End Model Selector] | [Model] CLKIN_533 Model_type Input | [Receiver Thresholds] removed [Derate_min] Slew_dc_vref_tangental 10.0 -45ps 2.0 -45ps 1.0 0. .50 125ps .40 188ps .1 200ps [End Derate_min] | [Derate_max] Slew_vref_ac_tangential 10.0 125ps 2.0 125ps 1.0 0. .50 -110ps .40 -175ps .1 -200ps [End Derate_max] [End Model] | [Diff_model] CLKIN_DIFF_533 Model_type Pseudo_Differential_Input Active_high_model CLKIN_533 Active_low_model CLKIN_533 | [Impedance_model] Zo 50 45 55 Zo_diff 100 90 110 C_comp 1.39pF 1.26pF 1.52pF C_comp_diff 1.10pF 1.01pF 1.19pF [End Impedance_model] | [Algorithmic Model] Executable Windows_VisualStudio_32 clkin_diff_533.dll clkin_diff_533.ami [End Algorithmic Model] | [External Model] ? [End External Model] | [Receiver Thresholds] Vcross_low = 0.675V | Minimum common mode voltage at differential signal crossing 0V Vcross_high = 1.125V | Maximum common mode voltage at differential signal crossing 0V Vcm_max = 1.35V | Maximum common mode voltage Vdiff = 250mV Vdiff_ac = 500mV Vdiff_dc = 250mV Tdiffslew_max_dc_ac = 5.000ns Tdiffslew_min_dc_ac = .1ns [End Receiver Thresholds] | [Derate_min] Slew_dc_vref | Derate min delay as function of dc_vref slew rate 4.0 0.0ps 2.0 0.0ps 1.5 -30ps 1.0 -60ps 0.1 -60ps [End Derate_min] | [Derate_max] Slew_vref_dc | Derate max delay as function of vref_dc slew rate 4.0 0.0ps 2.0 0.0ps 1.5 30ps 1.0 60ps 0.1 60ps [End Derate_max] | [tVAC] | Area required above Vdiff_ac to make derate tables valid 4.0 0.5pVs 2.0 0.1pVs 1.5 0. 1.0 0. 0.1 0. [End tVAC] | [Eye_template] | eye template, or eye aperture, consisting of time (in UI) and voltage .0 NA .1 NA .2 .1 .3 .3 .4 .4 .5 .45 .6 .4 .7 .3 .8 .1 .9 NA 1. NA [End Eye_template] | [End Diff_model] | [End]