[ibis-macro] I would like to consider how we would handle training a nibble ...
- From: Walter Katz <wkatz@xxxxxxxxxx>
- To: "IBIS-ATM" <ibis-macro@xxxxxxxxxxxxx>
- Date: Tue, 3 Sep 2019 20:54:45 -0400 (EDT)
Fangyi,
I understand your desire to have a capability to train all of the bits in a
nibble to have a common VREFDQ, and other Gain, Tx taps, Rx taps and skew. I
was not expecting this question since it has not come up with some IC
vendors, which is why I think it will be important to involve as many DDR5
controller and memory vendors in the process.
I do not want to complicate the DDR5 DQ Write Protocol more than I have to
at this point, but after we are in agreement on the single bit protocol, we
could develop a DDR5 DQ Nibble Write protocol which would allow 4 or 8 DQ
channels to each have their own Impulse Response and communicate
sequentially with a single BCI_ID file. I think it would be an interesting
challenge to devise such a protocol and would look forward to doing that
with you, along with controller and memory vendors that want/need this
capability.
Walter
Walter Katz
<mailto:wkatz@xxxxxxxxxx> wkatz@xxxxxxxxxx
Office 978.461-0449 x 133
Mobile 720.417-3762
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- » [ibis-macro] I would like to consider how we would handle training a nibble ... - Walter Katz
