VladimirWell, the first question is really, what is a "bit". Is a bit a complete symbol of length Bit_Time where the first bit is:
a) defined with respect to time=0 b) defined with respect to initial Tx differential crossing c) defined with respect to initial Rx differential crossing d) defined with respect to the initial clock_times value e) defined with respect to the EDA Tx stimulus f) defined with respect to the initial received bit arrival at the RxOnly Case e and f are unambiguous. But, case e doesn't make sense, because the receiver model has no idea long the channel delay might be at model development. In that case, f is the correct answer. However, the bit stream that is seen at the receiver is delayed by the transmitter and the channel, in which case, how do you know where the first received bit starts, since it may not include any transitions. The solution is for the EDA software to characterize the latency of the transmitter and channel, and add this to number of transmit bit times required before processing the receiver waveforms. If you accept this, then it does not matter that clock_times starts after the necessary Ignore_bits delay. This would mean that even after the correct delay period, the CDR has still not output a valid sample pulse. This is a bit error, and can happen when the received link amplitude is reduced to the point where the CDR does not lock. This is quite common in fiber and long copper cable interconnects.
Scott Dmitriev-Zdorov, Vladimir wrote:
Ignore_bits"This value tells the EDA platform how many bits of the AMI_Getwave output should be ignored"If clock times start from the value N1*Bit_interval and Ignore_Bits is equal N2, what is the specified behavior in cases:1. N1 < N2 (evident)2. N1 > N2 (it appears that the first defined sampling point requires that more bits will not go into processing)Does the spec need to detail this?
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