Hello everyone, This is an announcement for another release of the VHDL-AMS version of the IBIS macro model library. There is a very small change in it, I replaced the "<=" with "<" in the event controlled PWL sources for the input threshold detection equations. This was done to be consistent with the same code in the IBIS buffers and the Verilog-A version of the library. This is a very small change, but it makes the library more consistent and it also makes me feel better. :-) As usual, it is available from our web site: http://www.eda-stds.org/pub/ibis/macromodel_wip/element_lib/VHDL-AMS_element_library_SMASH_test.zip The Verilog-A version has not been effected by this change, which is also available at our web site: http://www.eda-stds.org/pub/ibis/macromodel_wip/element_lib/Verilog-A_element_library_HSPICE_test.zip The only thing I can think of that still needs to be finished is the documentation, which I hope will follow soon. Please try it, and let me know if you find any problems, bugs, etc... Thanks, Arpad ======================================================================== --------------------------------------------------------------------- IBIS Macro website : http://www.eda.org/pub/ibis/macromodel_wip/ IBIS Macro reflector: //www.freelists.org/list/ibis-macro To unsubscribe send an email: To: ibis-macro-request@xxxxxxxxxxxxx Subject: unsubscribe