[ibis-macro] Minutes for the October 7,14,21 ibis-atm meetings
- From: "Mike LaBonte (milabont)" <milabont@xxxxxxxxx>
- To: "IBIS-ATM" <ibis-macro@xxxxxxxxxxxxx>
- Date: Tue, 28 Oct 2008 14:21:12 -0400
Minutes for the October 7,14,21 ibis-atm meetings are attached.
Mike
IBIS Macromodel Task Group
Meeting date: 21 October 2008
Members (asterisk for those attending):
Ambrish Varma, Cadence Design Systems
Anders Ekholm, Ericsson
* Arpad Muranyi, Mentor Graphics Corp.
Barry Katz, SiSoft
* Bob Ross, Teraspeed Consulting Group
Brad Brim, Sigrity
Brad Griffin, Cadence Design Systems
David Banas, Xilinx
Donald Telian, consultant
Doug White, Cisco Systems
Essaid Bensoudane, ST Microelectronics
Fangyi Rao, Agilent
Ganesh Narayanaswamy, ST Micro
Gang Kang, Sigrity
Hemant Shah, Cadence Design Systems
Ian Dodd, Agilent
Joe Abler, IBM
* John Angulo, Mentor Graphics
John Shields, Mentor Graphics
Ken Willis, Cadence Design Systems
Kumar
Lance Wang, Cadence Design Systems
Luis Boluna, Cisco Systems
* Michael Mirmak, Intel Corp.
* Mike LaBonte, Cisco Systems
Mike Steinberger, SiSoft
* Mustansir Fanaswalla, Xilinx
Patrick O'Halloran, Tiburon Design Automation
Paul Fernando, NCSU
* Pavani Jella, TI
* Radek Biernacki, Agilent (EESof)
* Randy Wolff, Micron Technology
Ray Comeau, Cadence Design Systems
Richard Mellitz, Intel
Richard Ward, Texas Instruments
Sam Chitwood, Sigrity
Sanjeev Gupta, Agilent
Shangli Wu, Cadence Design Systems
Sid Singh, Extreme Networks
Stephen Scearce, Cisco Systems
Steve Pytel, Ansoft
Syed Huq, Cisco Systems
Syed Sadeghi, ST Micro
* Terry Jernberg, Cadence Design Systems
Todd Westerhoff, SiSoft
Vikas Gupta, Xilinx
Vuk Borich, Agilent
* Walter Katz, SiSoft
Zhen Mu, Cadence Design Systems
-----
Opens:
- None
--------------------------
Call for patent disclosure:
- No one declared a patent.
-------------
Review of ARs:
- Walter prepare presentation on final stage proposal
- Arpad send Fangyi Rao presentation to Mike L for posting
- Done
- Arpad will sent a notice
- Arpad: Write parameter passing syntax proposal (BIRD draft)
for *-AMS models in IBIS that is consistent with the
parameter passing syntax of the AMI models
- TBD
- TBD: Propose a parameter passing syntax for the SPICE
- [External ...] also?
- TBD
- Arpad: Review the documentation (annotation) in the macro libraries.
- Deferred until a demand arises or we have nothing else to do
-------------
New Discussion:
Michael M gave a Synopsys update:
- We have cleared 6 of 7 legal hurdles
- It should be approved this week
- Synopsys provided technical feedback to us:
- Todd has a copy of this
- Edits will be made once permission is granted
Walter presented his slides "Final Stage Subckt":
- Slide 2: Michael M proposal:
- IBIS B element with Freq-Volt dependent C_comp at pad
- Michael M had also proposed parameterized RC ladder circuit model
- Arpad: Would the B element include original C_comp?
- Walter: No, all C_comp would be in the new block
- Box with B element should mention "C_comp removed"
- Slide 3: Walter's proposal:
- The Final Stage subckt has 2 pad nodes:
- The Pad_IBIS connects to the B element
- The Pad goes to the outside world
- The Final stage has Stim, En, Vdd, Vss nodes
- SiSoft has found certain features necessary:
- s-param models
- These connect Pad_IBIS to Pad
- Stim, En, Vdd, Vss ports are not used
- Arpad: Wouldn't this make it non-LTI?
- Walter: It doesn't matter here
- This enables statistical models
- Slide 4: Differential models
- The Final Stage has 2 B elements, 4 pad nodes
- The Stim, En, Vdd, Vss ports connect to each block
- Also present is a Vcm node (common mode voltage)
- This enables true differential model using 2 B elements
- Slide 5: Differential Rx model
- Same as Differential Tx, but with no Stim or En
- Arpad: This can be done with [External Circuit]
- Walter: [External Circuit] can't have I-V curves
- This can support s-param models
- Michael M: John had suggested s-param within [External Circuit]
- John: You also need the B element
- Arpad: Not sure if I-V tables are excluded with [External Circuit]
- John: It is excluded
- Maybe the BIRD for this should be revived
- Michael M: Are we building mansion-style extensions on a shack?
- Maybe we need to start clean
- This may be too complicated to see it through
- Radek: What about V-T tables?
- Walter: It uses good ol' IBIS models (except C_comp)
- Maybe "IBIS IV" is confusing (Walter changed the slide to just "B element")
- Arpad: Are V-T tables needed for Hi-Z,Lo-Z, etc. transitions?
- Walter: IBIS was not designed for those transitions
- The proposal captures the dominant behavior
- It is an incremental change
- Bob: One assumption is that this has more impact on Rx
- But technically we should de-embed this load from V-T tables in the Tx
- Michael M: With the original approach the model extractor didn't worry
about this detail
- We would model C_comp at the pad looking in
- The de-embeding requirement would make model making more difficult
- Walter: Without changes IBIS may become irrelevant for high speed
- Arpad: Which is better, algorithmic or SPICE-like?
- Walter: It may be a subset of HSPICE, but we can add other elements
Walter showed a Final_Stage_Subckt syntax description:
( Walter was disconnected for a minute )
- The syntax adds the Final_Stage_Subckt IBIS keyword
- There would be rules for the SPICE contents
- Arpad: Why not use [External Circuit]?
- Walter: That is fine as long as it has the described functionality
- The differential circuit includes V_Shunt for pad pass-through
- Arpad: We should ask ourselves what can be done with [External Circuit]
- John: I can present something like that
- Arpad: Is this simpler than a mansion on a shack?
- Michael M: We have to insure this does not conflict with other proposals
- Arpad: We might need to add more controlled sources
- Arpad: We seem to be returning to keyword explosion
- Walter: Some enhancements have interfered with IBIS
- Package additions, [External Model] are fundamentally flawed
- AMD handles packages well
- With this addition IBIS can become more relevant again
- The best part of IBIS remains the B element and pin information
- Arpad: So we should get rid of newer IBIS features and use subckts?
- Walter: Yes, industry needs this
- Michael M: Who is the industry?
- We have to be careful in saying what is useful
- We have more EDA representation than IC in this group
- Walter: That is a fair critique
- Arpad: How do we get a correct view?
- Randy: We have been testing the effects of lossy C_comp
- So far there is no noticable difference in the results
- Walter: Effects begin at 3GHz
- Arpad's 3D graph shows effects starting at 5GHz
- Arpad: What do we discuss next week?
- John could summarize his BIRD idea
AR: John prepare summary of [External Circuit] enhancements for next meeting
Next meeting: 28 October 2008 12:00pm PT
-----------
IBIS Macromodel Task Group
Meeting date: 07 October 2008
Members (asterisk for those attending):
Ambrish Varma, Cadence Design Systems
Anders Ekholm, Ericsson
* Arpad Muranyi, Mentor Graphics Corp.
Barry Katz, SiSoft
* Bob Ross, Teraspeed Consulting Group
Brad Brim, Sigrity
Brad Griffin, Cadence Design Systems
David Banas, Xilinx
Donald Telian, consultant
Doug White, Cisco Systems
Essaid Bensoudane, ST Microelectronics
* Fangyi Rao, Agilent
Ganesh Narayanaswamy, ST Micro
Gang Kang, Sigrity
Hemant Shah, Cadence Design Systems
* Ian Dodd, Agilent
Joe Abler, IBM
* John Angulo, Mentor Graphics
John Shields, Mentor Graphics
Ken Willis, Cadence Design Systems
Kumar
Lance Wang, Cadence Design Systems
Luis Boluna, Cisco Systems
Michael Mirmak, Intel Corp.
* Mike LaBonte, Cisco Systems
Mike Steinberger, SiSoft
Mustansir Fanaswalla, Xilinx
Patrick O'Halloran, Tiburon Design Automation
Paul Fernando, NCSU
* Pavani Jella, TI
* Radek Biernacki, Agilent (EESof)
* Randy Wolff, Micron Technology
Ray Comeau, Cadence Design Systems
Richard Mellitz, Intel
Richard Ward, Texas Instruments
Sam Chitwood, Sigrity
Sanjeev Gupta, Agilent
Shangli Wu, Cadence Design Systems
Sid Singh, Extreme Networks
Stephen Scearce, Cisco Systems
Steve Pytel, Ansoft
Syed Huq, Cisco Systems
Syed Sadeghi, ST Micro
Terry Jernberg, Cadence Design Systems
* Todd Westerhoff, SiSoft
Vikas Gupta, Xilinx
Vuk Borich, Agilent
* Walter Katz, SiSoft
Zhen Mu, Cadence Design Systems
-----
Opens:
--------------------------
Call for patent disclosure:
- No one declared a patent.
-------------
Review of ARs:
- Arpad: Write parameter passing syntax proposal (BIRD draft)
for *-AMS models in IBIS that is consistent with the
parameter passing syntax of the AMI models
- TBD
- TBD: Propose a parameter passing syntax for the SPICE
- [External ...] also?
- TBD
- Arpad: Review the documentation (annotation) in the macro libraries.
- Deferred until a demand arises or we have nothing else to do
-------------
New Discussion:
Todd reported on the latest meeting with Synopsys:
- We asked for permission to use the syntax and copy from their documentation
- They asked if there would be additional changes requested
- They will ask their legal department
- No concerns are expected
- Mike L: Will they want to approve it word for word?
- Todd: No one knows
- Arpad: So now do we have permission to put it on our web site?
- Todd: Probably, but we should confirm with Michael M
AR: Todd check on permission for Mike L to post Interconnect SPICE syntax
We took a look at the new C_comp circuit proposal
- Slide 19 was shown
- Mike L: Any change should address state dependency well
- Simulators will have a hard time if different circuits are used
- Arpad: The transition between states is the hardest part
- Walter: This should replace C_comp, not be an addition
- It should be an external subckt
- The nodes should be:
- 1 Ground
- 2 Rail voltage
- 3 Pad IV side
- 4 Pad Pad side
- 5 Enable
- IBIS can't really handle enable on/off
- Mike L: agree
- Arpad: agree
- Mike L: How about a stimulus port for logic state dependence?
- Walter: Agree, but circuits don't have to use it
- Arpad: Maybe we should add features enable on/off accuracy to IBIS
- Mike L: For example, [Enable Waveform] and [Disable Waveform]
- Radek: This changes from simple C_comp to more complicated circuit
- Why not model it with a non-linear capacitance?
- Walter: Michael M showed this on one slide
- Mike L: Tables are OK for V dependence, RC ladder for F dependence
- Walter: Using a circuit avoids the need for more keywords
- Todd: How would non-linear capacitance work?
- Radek: We would create a charge vs. voltage model
- Arpad: The fixed circuit proposed can model frequency dependency
- Time domain simulators can't handle frequency models
- Todd: This has to work in as many simulators as possible
- Radek: Voltage dependency is needed too
- Randy: Michael M proposed circuits selectable by voltage
- Fangyi: Changing elements dynamically is hard for simulators
- Arpad: The circuit shown works equally well in time and frequency domains
- Arpad: Laplacian approaches have been tried:
- One circuit obeyed charge conservation, one did not
- Walter: Michael M was using voltage controlled R and C
- Arpad: Not sure if they were voltage controlled
- Walter: These are not LTI
- A frequency based solution that is LTI might be desirable
- Fangyi: We can have voltage dependent or frequency dependent, but not both
- Arpad: We have to decide what it means to change C plates
- Fangyi: Can expand C model into higher order derivative
- i = C*dv/dt + C2*dv2/dt = ...
- We can represent V dependence with a Laplacian
- Bob: How do we get the coefficients?
- It is not easy
- Radek: We need to understand the problem we are modeling
- Mike L: The "ribbon plot" on slide 13 shows the problem
- Fangyi: A higher order model can represent anything
- Arpad: Can we have a presentation on this?
- Fangyi: Not sure how much can be done by next week
- Walter: Is V on slide 13 pad V or rail V?
- Arpad: It is pad V
- Walter: There appears to be a huge change at 1MHz
- V dependence is small
- Radek: That appears to be a linear effect
AR: Fangyi prepare presentation on high order C modeling
Arpad: We still need to model state dependency
- One model is a combination of series RC and parallel RC
- May be able to dig up some material on this
- Walter: We can't be sure that V dependency is a major factor
AR: Arpad try to find material on series-parallel RC models
Next meeting: 14 October 2008 12:00pm PT
-----------
IBIS Macromodel Task Group
Meeting date: 14 October 2008
Members (asterisk for those attending):
Ambrish Varma, Cadence Design Systems
* Anders Ekholm, Ericsson
* Arpad Muranyi, Mentor Graphics Corp.
Barry Katz, SiSoft
* Bob Ross, Teraspeed Consulting Group
Brad Brim, Sigrity
Brad Griffin, Cadence Design Systems
* David Banas, Xilinx
Donald Telian, consultant
Doug White, Cisco Systems
Essaid Bensoudane, ST Microelectronics
* Fangyi Rao, Agilent
Ganesh Narayanaswamy, ST Micro
Gang Kang, Sigrity
Hemant Shah, Cadence Design Systems
Ian Dodd, Agilent
Joe Abler, IBM
John Angulo, Mentor Graphics
John Shields, Mentor Graphics
Ken Willis, Cadence Design Systems
Kumar
Lance Wang, Cadence Design Systems
Luis Boluna, Cisco Systems
Michael Mirmak, Intel Corp.
* Mike LaBonte, Cisco Systems
Mike Steinberger, SiSoft
* Mustansir Fanaswalla, Xilinx
Patrick O'Halloran, Tiburon Design Automation
Paul Fernando, NCSU
* Pavani Jella, TI
Radek Biernacki, Agilent (EESof)
* Randy Wolff, Micron Technology
Ray Comeau, Cadence Design Systems
Richard Mellitz, Intel
Richard Ward, Texas Instruments
Sam Chitwood, Sigrity
Sanjeev Gupta, Agilent
Shangli Wu, Cadence Design Systems
Sid Singh, Extreme Networks
Stephen Scearce, Cisco Systems
Steve Pytel, Ansoft
Syed Huq, Cisco Systems
Syed Sadeghi, ST Micro
Terry Jernberg, Cadence Design Systems
* Todd Westerhoff, SiSoft
Vikas Gupta, Xilinx
Vuk Borich, Agilent
* Walter Katz, SiSoft
Zhen Mu, Cadence Design Systems
-----
Opens:
--------------------------
Call for patent disclosure:
- No one declared a patent.
-------------
Review of ARs:
- Todd check on permission for Mike L to post Interconnect SPICE syntax
- Done
- We will wait to hear from Synopsys legal
- Fangyi prepare presentation on high order C modeling
- Done
- Arpad try to find material on series-parallel RC models
Done
- Arpad: Write parameter passing syntax proposal (BIRD draft)
for *-AMS models in IBIS that is consistent with the
parameter passing syntax of the AMI models
- TBD
- TBD: Propose a parameter passing syntax for the SPICE
- [External ...] also?
- TBD
- Arpad: Review the documentation (annotation) in the macro libraries.
- Deferred until a demand arises or we have nothing else to do
-------------
New Discussion:
Arpad showed his June 2004 IBIS summit presentation:
- "I-V curve linearity and buffer impedance"
- Slide 5:
- Zac is the tangent line
- Zdc is the end-to-end slope
- Zac and Zdc differ
- Slide 10:
- At low frequency the curve matches slide 5
- The curve does not look right at higher frequencies.
- This is expained by Miller capacitance coupling the pre-driver
- Slide 12:
- Adding Miller capacitance improves accuracy
Arpad showed his June 2001 IBIS summit presentation:
- "High Accuracy Behavioral Modeling for Frequency and Time Domain Simulations"
- Transfer functions can be modeled with G elements
- A simple RCG circuit can model voltage dependence
- The frequency domain response is good
- David: Was this ever proposed for IBIS?
- Arpad: It would have involved complex number capability
- The RC ladder circuit is not magic, it just happens to model closely
Fangyi showed his document:
- "Modeling Nonlinearity in Response Function"
- Time-independent equation can be generalized to be time dependent
- A derivative expansion method is used
- Two nonlinear no-memory functions can be combined
- With memory functions a Wiener series can be used
- The memory function is used to model voltage dependency
- We need to measure frequency response using a time varying V source
- Arpad: Would time domain simulation be used to generate this data?
- Fangyi: Two frequency sweeps are needed:
- input sweep
- bias sweep
- Bob: Is output measured as amplitude and phase?
- Yes
- Arpad: So the simulator would implement the equations, and the model
would have only coefficients?
- Yes
- Fangyi: The Weiner representation is the important part
- Arpad: Nonlinearity captures the shape of the I-V curve
- Arpad: What happens when the buffer switches from one I-V to the other?
Arpad: How does this compare to Michael M proposal?
Walter showed slide 11 from Arpad's June 2004 presentation:
- This doesn't show the C_comp that is usually present
- Walter showed a slide "Isolate IBIS IV from Final Stage"
- Michael M circuit shows an RC final stage
- May have some voltage dependence
- Final stage at high speeds can look like a low pass filter
- At 3GHz+ we are seeing this
- The proposals we have seen are ways of modeling this final stage
- The final stage can be a box
- Arpad: It depends on how radically we want to move away from IBIS today
- This may run out of steam eventually
- Would prefer to have control over actual buffer impedance
- Walter: Current IBIS not sufficient above 5GHz
- Elements beyond RC needed to model final stage
- Can be implemented in HSPICE or IBIS Interconnect SPICE
- We have heard 4 solutions so far
- A final stage box can implement all
- Arpad: The best match would be the model itself
- Walter: This would be the best behavioral approach
- Walter: The final stage subckt would have stimulus, enable, and power nodes
AR: Walter prepare presentation on final stage proposal
AR: Arpad send Fangyi Rao presentation to Mike L for posting
Next meeting: 14 October 2008 12:00pm PT
-----------
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