[ibis-macro] Minutes from the 11 Nov 2014 ibis-atm meeting
- From: Mike LaBonte <mike@xxxxxxxxxxx>
- To: 'IBIS-ATM' <ibis-macro@xxxxxxxxxxxxx>
- Date: Tue, 11 Nov 2014 17:01:51 -0500
Minutes from the 11 Nov 2014 ibis-atm meeting are attached.
Mike
IBIS Macromodel Task Group
Meeting date: 11 November 2014
Members (asterisk for those attending):
Altera: * David Banas
ANSYS: * Dan Dvorscak
* Curtis Clark
Avago (LSI) Xingdong Dai
Cadence Design Systems: * Ambrish Varma
Brad Brim
Kumar Keshavan
Ken Willis
Ericsson: Anders Ekholm
IBM Steve Parker
Intel: Michael Mirmak
Keysight Technologies: * Fangyi Rao
* Radek Biernacki
Maxim Integrated Products: Hassan Rafat
Mentor Graphics: * John Angulo
* Arpad Muranyi
Micron Technology: * Randy Wolff
Justin Butterfield
QLogic Corp. James Zhou
Andy Joy
eASIC Marc Kowalski
SiSoft: * Walter Katz
* Todd Westerhoff
* Mike LaBonte
Synopsys Rita Horner
Teraspeed Consulting Group: Scott McMorrow
Teraspeed Labs: * Bob Ross
(Note: Agilent has changed to Keysight)
The meeting was led by Arpad Muranyi.
------------------------------------------------------------------------
Opens:
- Arpad: Are there any upcoming meeting dates to avoid?
- We previously found none.
--------------------------
Call for patent disclosure:
- None
-------------
Review of ARs:
- Mentor, Keysight, Cadence investigate TX Dj issues.
- Walter: I would like to discuss this.
- I proposed a BIRD to clarify, but will not pursue it.
- IBIS 6.0 is sufficient.
- This is done.
- Walter send BIRD on C_comp enhancements.
- Final Stage Subckt has been posted.
- Ambrish ask Bob for written feedback on BIRD 147.1
- Done.
- Todd produce slides for co-optimization requirements discussion next week.
- In progress.
- Arpad to review IBIS spec for min max issues.
- In progress.
-------------
New Discussion:
C_comp:
- Arpad showed "Enhancing C_comp for IBIS".
- slide 2:
- Arpad: A circuit for this is available to experiment with.
- This uses a copy of the pad voltage and C_comp capacitor.
- It is not connected to the pad, it is just to measure the C_comp current
profile.
- The "real" circuit has a current source to back that effect out.
- slide 3:
- Arpad: This is the same circuit but with an ISS subckt.
- slide 4:
- Arpad: An internal test circuit can obtain the compensation current.
- slide 5:
- Arpad: One question is where the compensation point should be.
- It might be the buffer node, a die node or the pad node.
- David: There is no definition of where C_comp is?
- Arpad: In the old days the buffer was thought of as being at the pad.
- David: Wouldn't we have to stick with that interpretation?
- Arpad: A bigger question is how much to compensate for.
- We need to read the spec again.
- Randy: We have to think about the idea of having the buffer separate from
the pad.
- Walter: With a large C_comp you might get a long rise time.
- The V/T has that rise time in it.
- The k(t) function has a faster rise time.
- Compensation has to affect the shape of the k(t) curve.
- Arpad: Sometimes the speedup can be negative in time.
- David: Is this caused by unrealistic C_comp vs. the V/T?
- Walter: It can be bad C_comp or V/T.
- C_comp has to be typ/min/max.
- Arpad: We should focus on how to address this in the spec.
- Questions like if die interconnect metal is included.
- We must not double count.
- slide 2:
- Bob: Does this cancel out C_comp?
- Arpad: Vpad actually needs to have the V9t) voltage.
- Radek: We have to be precise in the spec.
- It is a two terminal circuit but it might also specify the measurement
point for C_comp.
- Arpad: This is just a concept model.
- slide 5:
- Arpad: On die interconnect is usually not included.
- Specifying compensation location would be helpful.
- Bob: Would the on die interconnect be different for each model?
- Arpad: How does this compare with Walter's Final Stage Subckt proposal?
- Walter: Your circuit is parallel as opposed to series.
- The Final Stage Subckt is simple, just for ESD diodes.
- It's easy for receivers.
- One question is how to allow this on a driver.
- The EDA tool would use V/T curves for correction, not C_comp.
- Saying where the measurement point lies requires coordination between EDA
and model makers.
- Arpad: The ISS subckt can be both shunt and series?
- Walter: I did it that way.
- The "buf" node is straightforward.
- Adding a series ISS introduces yet another node.
- The ISS subckt will have an effective capacitance that will have to be
considered.
- I can't find in IBIS 6.0 where V/T is to be measured.
Double quote BIRD draft:
- Arpad: The BIRD disallows extended-ASCII.
- Ambrish: I did not intentionally add any illegal characters.
- Mike suggested Microsoft tools were adding them
- Mike: We could simply allow extended ASCII for IBIS comments.
- Arpad: It might be complicated to describe.
- Bob: We might allow extended quotes.
- Arpad: Could the parser find them and fix them?
- Bob: We probably should cover this in the IBISCHK document.
- Mike: IBISCHK is read-only today, we would have to be careful about letting
it write files.
- Arpad: We could offer a simple script to fix these files.
- Bob: EDA tools could do that too.
- Some of these tools remove tabs.
- Arpad: Tabs are allowed, but discouraged.
- Radek: There could be problems created by having different quote types in
different files.
AR: Arpad send Double Quote BIRD draft presentation with updates to Mike for
posting.
-------------
IBIS Interconnect SPICE Wish List:
1) Simulator directives
Other related posts:
- » [ibis-macro] Minutes from the 11 Nov 2014 ibis-atm meeting - Mike LaBonte
