[ibis-macro] Minutes from the 11 Sep 2012 ibis-atm meeting

  • From: Mike LaBonte <mike@xxxxxxxxxxx>
  • To: IBIS-ATM <ibis-macro@xxxxxxxxxxxxx>
  • Date: Tue, 18 Sep 2012 10:04:14 -0400

Minutes from the 11 Sep 2012 ibis-atm meeting are attached.

Mike
                                             
IBIS Macromodel Task Group

Meeting date: 11 Sep 2012

Members (asterisk for those attending):
Agilent:                    * Fangyi Rao
                            * Radek Biernacki
Altera:                     * David Banas
                              Julia Liu
                              Hazlina Ramly
Andrew Joy Consulting:        Andy Joy
ANSYS:                        Samuel Mertens
                            * Dan Dvorscak
                            * Curtis Clark
                              Steve Pytel
                              Luis Armenta
Arrow Electronics:            Ian Dodd
Cadence Design Systems:       Terry Jernberg
                            * Ambrish Varma
                              Feras Al-Hawari
Cavium Networks:              Johann Nittmann
Celsionix:                    Kellee Crisafulli
Cisco Systems:                Ashwin Vasudevan
                              Syed Huq
Ericsson:                     Anders Ekholm
IBM:                          Greg Edlund
Intel:                      * Michael Mirmak
Maxim Integrated Products:    Mahbubul Bari
Mentor Graphics:            * John Angulo
                              Zhen Mu
                            * Arpad Muranyi
                              Vladimir Dmitriev-Zdorov
Micron Technology:            Randy Wolff
                            * Justin Butterfield
NetLogic Microsystems:        Ryan Couts
Nokia-Siemens Networks:       Eckhard Lenski
QLogic Corp.                * James Zhou
Sigrity:                    * Brad Brim
                              Kumar Keshavan
                              Ken Willis
SiSoft:                     * Walter Katz
                              Todd Westerhoff
                              Doug Burns
                            * Mike LaBonte
Snowbush IP:                  Marcus Van Ierssel
ST Micro:                     Syed Sadeghi
Teraspeed Consulting Group:   Scott McMorrow
                            * Bob Ross
TI:                           Casey Morrison
                              Alfred Chong
Vitesse Semiconductor:        Eric Sweetman
Xilinx:                       Mustansir Fanaswalla
                              Ray Anderson

Note: The name "Abhishek Munjal" appeared in NetMeeting but no corresponding 
voice was heard.

The meeting was led by Arpad Muranyi

------------------------------------------------------------------------
Opens:

- None

--------------------------
Call for patent disclosure:

- None

-------------
Review of ARs:

- Michael M provide examples to show what IC vendors need
  - Done with part 1
  - Need questions answered to do part 2

-------------
New Discussion:

Michael M showed "Package Model Format Needs":
- Michael M: This is part 1
- slide 3:
  - Michael M: We address two types of analysis and three user segments
    - We try not to put a large burden on any single segment
- slide 4:
  - Michael M: For post-layout user may have specific nets to look at
    - They may not have been identified by name
    - May want to look at signals with crosstalk over some threshold
    - Besides format, there is a question if the same data is useful pre and 
post layout
- slide 5:
  - Michael M: Three ways to look at the problem:
    - Full model
    - Small swath model
    - Many small models
  - Need to look at how each user sees each type
  - Swathed models will be hard for EDA vendors to develop
- slide 6:
  - Michael M: The model maker controls the destiny of the other two
    - The ideal case is where the end user controls what is extracted
    - That will be hard to do
  - Arpad: Why is that difficult?
  - Michael M: The person controlling distribution limits what it will cover
    - Small models are more work to create, easy to use
    - Large models are easy to make, hard to use
- back to slide 5:
  - Walter: On large models the through paths must be accurate
    - There are limited coupling paths that must be examined
    - Sparse formats will reduce file size
    - The EDA tool can choose what to use
    - S20p models can be quickly extracted from s1000p models
  - Michael M: That is entirely in the context of s-parameters
    - Am I automatically limited?
  - Walter: ???
  - Michael M: Then the extraction tool should be able to use coupling info for 
that
  - James: For most buses the highest pin count is about a thousand
    - Probably need 1 to 5 aggressors max
    - The standard should allow arbitrarily large models
    - Tools should be able to make it easy for end users
  - Michael M: We don't want the standard to eliminate possibilities, agree
    - But some customers create "unusual" designs where crosstalk is more of a 
problem
    - Time domain models other than s-parameters are an issue too
  - Walter: Some simulators have trouble with long chains of short s4ps
    - Package models should not have many of those
  - Michael M: For part 2 a swathed s12p example might be good
  - Walter: Some vendors deliver s4ps and expect them to be combined
    - This might be an alternative to swathing
  - Brad: It's easy to violate passivity with those
  - James: It is easy to measure return losses and combine into an s16p
  - Radek: When we neglect far coupling we sacrifice accuracy
    - This has to be well understood
    - Usually we only have full matrices
  - Michael M: Has anyone tried creating an sZILLIONp model from lab data?
    - Equipment requires tricks to do that
  - Walter: It has been done up to 150
  - James: We have seen around 130

- Arpad: Have we seen this done?
- Michael M: I have not seen a case where sparse data is used for full 
simulation
- Arpad: Walter may have an example
- Walter: I emailed one, but it only has about 20 pins
  - Scott has also proposed creating s1000p models
- Michael M: We should err on the side of giving as much data as possible
  - Reducing data for specific applications may not help
- Walter: My format has no inherent size limitation
  - Model makers will be aware of tool limitations
- Arpad: BIRD 125 can be modified to meet these needs
  - We need to answer some questions before proceeding
- Michael M: The hybrid solution may be best
  - The existing spec has interactions that are hard to understanding
  - A simpler IBIS spec that connects pins/pads to other things would help
  - A pad keyword would be better
- Walter: I would like to show the email I sent
- Arpad: Maybe we should reorder our priorities first to get other BIRDs out of 
the way
  - We need to address the AMI analog model problem
  - Could packaging be handled by a subcommittee
- Michael M: The interconnect task group could come back
- Arpad and Walter liked the idea

AR: Michael M restart interconnect task group meetings Wednesdays 8am or 9am PT

Walter showed an example IBIS file and example package tree syntax:
- Walter described the tree syntax
- Walter: Corners might be limited to three, although more might be needed by 
some
  - This might be called a mixed model
- Walter showed a full package model example tree syntax
  - In this one each pin is a victim
  - It shows the power and ground pins
  - This is a simple, incremental change to IBIS
  - A separate file might also describe the on-die models
- James: Are these competing against each other?
- Walter: One might use one where there is crosstalk and another elsewhere
  - In pre-layout there may not be pin names
  - They are three views of the interconnect
- James: The semantics are different
- Walter: Yes

Arpad: Would interconnect meetings start tomorrow?
- Walter: I think we have to assume next week

- James: We have to consider the model maker burden of these syntaxes
  - For the user it may be hard to choose which model to use
  - End users should choose how many aggressors, etc.
- Walter: A full model would be the only source data needed
  - This single syntax allows any use we want
  - Brad Brim might want to add XY coordinates

-------------
Next meeting: 18 Sep 2012 12:00pm PT

Next agenda:
1) Task list item discussions

-------------
IBIS Interconnect SPICE Wish List:

1) Simulator directives

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