[ibis-macro] Minutes from the 13 Jan 2009 ibis-atm meeting
- From: "Mike LaBonte (milabont)" <milabont@xxxxxxxxx>
- To: "IBIS-ATM" <ibis-macro@xxxxxxxxxxxxx>
- Date: Wed, 14 Jan 2009 14:41:41 -0500
Minutes from the 13 Jan 2009 ibis-atm meeting are attached.
Mike
IBIS Macromodel Task Group
Meeting date: 13 January 2009
Members (asterisk for those attending):
Ambrish Varma, Cadence Design Systems
* Anders Ekholm, Ericsson
* Arpad Muranyi, Mentor Graphics Corp.
Barry Katz, SiSoft
* Bob Ross, Teraspeed Consulting Group
Brad Brim, Sigrity
Brad Griffin, Cadence Design Systems
* David Banas, Xilinx
Donald Telian, consultant
Doug White, Cisco Systems
* Eckhard Lenski, Nokia-Siemens Networks
Essaid Bensoudane, ST Microelectronics
Fangyi Rao, Agilent
Ganesh Narayanaswamy, ST Micro
Gang Kang, Sigrity
Hemant Shah, Cadence Design Systems
Ian Dodd, Agilent
Joe Abler, IBM
* John Angulo, Mentor Graphics
John Shields, Mentor Graphics
Ken Willis, Cadence Design Systems
Kumar
Lance Wang, Cadence Design Systems
Luis Boluna, Cisco Systems
Michael Mirmak, Intel Corp.
* Mike LaBonte, Cisco Systems
Mike Steinberger, SiSoft
* Mustansir Fanaswalla, Xilinx
Patrick O'Halloran, Tiburon Design Automation
Paul Fernando, NCSU
* Pavani Jella, TI
* Radek Biernacki, Agilent (EESof)
Randy Wolff, Micron Technology
Ray Comeau, Cadence Design Systems
Richard Mellitz, Intel
Richard Ward, Texas Instruments
Sam Chitwood, Sigrity
* Sanjeev Gupta, Agilent
Shangli Wu, Cadence Design Systems
Sid Singh, Extreme Networks
Stephen Scearce, Cisco Systems
Steve Pytel, Ansoft
Syed Huq, Cisco Systems
Syed Sadeghi, ST Micro
Terry Jernberg, Cadence Design Systems
Todd Westerhoff, SiSoft
Vikas Gupta, Xilinx
Vuk Borich, Agilent
* Walter Katz, SiSoft
Zhen Mu, Cadence Design Systems
------------------------------------------------------------------------
Opens:
--------------------------
Call for patent disclosure:
- No one declared a patent.
-------------
Review of ARs:
- Walter: Send color-coded version of his "Recommended course of action for
IBIS"
- Done
- Michael M: Confirm with Synopsys whether "used by permission" can be used
as the official indicator on relevant documents.
- Email from Michael M indicates no progress.
- Arpad: Write parameter passing syntax proposal (BIRD draft)
for *-AMS models in IBIS that is consistent with the
parameter passing syntax of the AMI models
- TBD
- TBD: Propose a parameter passing syntax for the SPICE
- [External ...] also?
- TBD
- Arpad: Review the documentation (annotation) in the macro libraries.
- Deferred until a demand arises or we have nothing else to do
-------------
New Discussion:
Arpad showed a copy of Walter's "Recommended course of action for IBIS":
- Bob: Items 3 & 4 should be moved to another committee
- Arpad asked about Ad Hoc Interconnect task group progress:
- Bob: The group is racing toward a conclusion to Touchstone 2.0:
- It includes 10 new keywords
- Reference impedance by port
- Adminstrative: #ports, etc
- Help to make the file more free format
- Reduce full matrix to half matrix
- Mixed mode order allows differential information
- Begin/End keywords allow for growth
- Sparse matrices have been pushed off to another release
- The project is years behind schedule
- The new spec may be submitted in March
- Arpad: items 3 & 4 can be taken up after Touchstone 2.0 is out
- IBIS Interconnect Spice would be next on our plate
Walter explained each letter item under #1:
- Differential Termination Subckt:
- Walter: Currently we can have a only resistor for this
- There are more complex terminations in use
- IBIS Interconnect Spice would make it easier
- Arpad: R_series, L_Series etc. are not sufficient?
- Walter: they are not
- Diff Std Load:
- Walter: This should include single ended loads
- The load for timing is not always a simple RLC
- We currently have Vmeas, Cref, Rref, Vref
- There are new differential keywords
- Common Mode Voltage:
- Use for Differential Termination Subckt
- This keyword gives the typ/min/max voltage
- It is a reference voltage, not termination power
- Bob: [Receiver Thresholds] has External_reference
- Walter: This is single ended only
- Simple N-tap FIR EQ for TX
- Walter: The TX filters in use are simple
- This would have the same behavior as the AMI TX model
- Mike L: There is some irony that a new keyword is proposed along
with a circuit language features to reduce new keywords
- Simple LTI Impedance model
- This would replace I/V curves
- Cookbook for differential buffers
- Arpad: Walter had an AR to examine the existing IBIS Cookbok
- Walter: It was written in 2000
- It is too complex, there is a better way
- The cookbook is hard to understand
- The proposal is for a cookbook using current IBIS keywords
- Walter has a document that could be made public
- Arpad: This could be made public as an IBIS summit presentation
- Walter: The cookbook should be revised
- Pavani: Agree, the cookbook is the best place for this
- Eckhard: We wrote the cookbook because of lack of guidance from vendors
- It can be difficult to get information needed for SPICE buffer models
- Industry standards
- Not much discussion on this
Arpad: IBIS Interconnect SPICE would help with a number of things
- Why not just use SPICE?
- Mike L: IBIS still offers "plug and play" capability
- IBIS Interconnect Spice seems OK if the circuits can be in the IBIS file
- Walter: We should assume IBIS Interconnect Spice exists and begin implementing
- Anders: Would like to see more timing model standards
- Mike L: This is related to the 1h [Specification] keyword proposal
- IBIS has trouble keeping up with industry standards
- Anders: We need derating, for example
- Walter: This is about setup/hold, pin-to-pin skews
- Does IBIS want to get into this?
- Timing is never IP-protected, and easily published
- Arpad: This is different from chip-to-chip (system) timing
- Walter: 1h is not about system timing
- It describes how to extract timing for a part
- This group should not address system timing
Arpad: Do we want incremental changes or starting over?:
- Eckhard: Incremental because we have to support old IBIS anyway
- We might need to deliver 2 IBIS models for each part
- Arpad: Tools may be able to co-simulate both
- Mike L: The IBIS Interconnect Spice based ideas would be a good start
- Several tasks here could be done in parallel
Arpad: We should look at prototypes for Walter's keywords
- BIRD format would be best
- Walter can show a list of keywords for all but 1g
- Bob: This should be ispread out across multiple BIRDs
- Walter: Disagree: A BIRD should implement what it takes to solve a problem
- Arpad: 1h does not seem related, so might be excluded along with 1g
AR: Walter draft BIRD proposal for new keywords
Next meeting: 20 January 2009 12:00pm PT
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