Minutes from the 17 July IBIS ATM task group meeting are attached.
IBIS Macromodel Task Group
Meeting date: 17 July 2018
Members (asterisk for those attending):
ANSYS: Dan Dvorscak
Curtis Clark
Cadence Design Systems: * Ambrish Varma
Brad Brim
Kumar Keshavan
Ken Willis
eASIC: David Banas
GlobalFoundries: Steve Parker
IBM Luis Armenta
Trevor Timpane
Intel: Michael Mirmak
Keysight Technologies: Fangyi Rao
* Radek Biernacki
Ming Yan
Stephen Slater
Mentor, A Siemens Business: John Angulo
* Arpad Muranyi
Micron Technology: Randy Wolff
* Justin Butterfield
SiSoft: * Walter Katz
Todd Westerhoff
* Mike LaBonte
SPISim: * Wei-hsing Huang
Synopsys: Rita Horner
Kevin Li
Teraspeed Consulting Group: Scott McMorrow
Teraspeed Labs: * Bob Ross
The meeting was led by Arpad Muranyi. Justin Butterfield took the minutes.
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Opens:
- Mike stated he will look into the issues with Webex, as the Quality and ATM
meetings both had issues logging in [AR].
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Review of ARs:
- None.
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Call for patent disclosure:
- None.
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Review of Meeting Minutes:
- None.
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New Discussion:
Arpad noted that we untabled the algorithmic modeling for single ended
applications topic last time, and he combined this with the clock forwarding
topic on the agenda.
Input thresholds/measurement:
Arpad asked if Walter had any updates on his input threshold/eye diagram
measurement proposal. Walter stated he would like to get feedback from the
major EDA vendors on their interest in the proposal. Walter shared his
presentation on the DDR4/DDR5 input threshold requirements. SiSoft has a
propriety way of doing the input thresholds, but he would like to see an
industry standard way. Ambrish asked if this is a comprehensive list of things
we want in the specification or the least we need to include. Walter replied
that this addresses the minimum requirements for DDR4/DDR5. Ambrish stated we
should prioritize and asked what are the most necessary aspects. Walter stated
that an EDA tool can decide what to support. Ambrish said he is interested in
the approach from others and Cadence was considering a proposal on this.
Walter stated he would like to get consensus from all the EDA vendors that we
want to move forward. If we can get a consensus, he would submit a proposal
based on how SiSoft does it. Cadence and Keysight could also summit similar
proposals, and we can work out the details.
Radek asked about the include file for the specifications, and if we can add a
file to address the thresholds. Walter stated that SiSoft has an include file,
which can be reused and defines [Model Spec] like parameters based on the JEDEC
specification name. There would be some details to work out, but this could be
a good solution.
Ambrish asked if items 2 and 3 on Walter's list are critical. Walter replied
that he would like to do all of them. Ambrish asked if it is essential to
support DDR4/DDR5 or if it is a nice to have. Walter stated Randy would like
to have one IBIS file for every EDA vendor to use. Walter commented that when
we get consensus then we can proceed, and his goal was to introduce the subject.
Bob noted that Arpad had a proposal to reference the standard, and the EDA tool
can handle the details of the threshold measurements. Walter commented he
would like to have the signalling standard in a computer readable format.
Arpad asked if you have a model with a specific standard, the EDA tool would
know how to evaluate the results. He views this as similar to the back channel
proposal. This might simplify our work, as we would not have to go into the
details of each standard. Walter stated that this would work for him. Arpad
noted that this would need a new BIRD to name the standard. Walter thought we
could introduce a new "Standard" keyword with a single argument. Arpad asked
Ambrish his thoughts on this. Ambrish replied that he would have to think
about it. Ambrish stated his concern is if the IBIS Specification is useful
without this. He mentioned the need for IBIS-AMI for DDR4/DDR5. Arpad stated
that the IBIS-AMI for DDR4/DDR5 is separate question. Walter stated that the
current discussion is related to only the DDR4/DDR5 input thresholds, and the
IBIS-AMI for single-ended is a separate discussion.
Bob noted that models can be used with different standards. Walter stated in
the case of memory, they are either one standard or the other, unlike SERDES
which are configurable. The exception could be in the case of FBGAs. Bob
noted there are workarounds. Bob commented a separate file with the standard
values could be useful.
Arpad asked how we should proceed. Walter commented we could proceed with just
declaring the standard in the IBIS file. Ambrish asked if Walter could share
an example of how SiSoft does this. Walter showed an example of how the
"|Sisoft" parameters that they add as an include file work. He also showed how
these work across different speed grades, but noted there could be other ways
to do the speed grade selection. Radek asked what the intent is. Walter
replied he would like to have a BIRD with the statements as
keywords/subparameters. Arpad stated his proposal would point to the standard,
and the EDA tool would handle the rest. Walter stated he would be okay with
this. Arpad asked if Radek had any feedback on this proposal. Radek stated he
would have to think about it and discuss it internally.
Single ended applications of algorithmic modeling:
Walter thought we should start discussing algorithmic modeling for single ended
applications and how IBIS should address the different rise and fall times.
Radek agreed this is an issue we need to discuss. Walter stated that he
suspects most EDA tools have a solution for this. Arpad commented one way to
solve this problem is to increase the number of impulse responses that the AMI
standard supports. Ambrish stated that this in the realm of the EDA tool.
Walter agreed that it is not necessary to change specification. Arpad asked if
the DLL format would need to change. Ambrish commented that what we have today
should be sufficient to model the different rise and fall times. Walter agreed
with Ambrish that rise and fall time differences can be handled by the EDA
tool. Walter stated it is up to the EDA tool to meld the step responses for
rise and fall response. Wei-hsing commented that potentially the model maker
can call the impulse response twice. Ambrish noted there are many different
ways of creating the impulse response other than differentiating the step
response.
- Mike: Motion to adjourn.
- Ambrish: Second.
- Arpad: Thank you all for joining.
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Next meeting: 24 July 2018 12:00pm PT
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IBIS Interconnect SPICE Wish List:
1) Simulator directives
