Minutes from the 18 Feb 2014 ibis-atm meeting are attached. Also, the example IBIS file shown by Walter Katz in the meeting has been placed in the work archive <http://www.eda.org/ibis/macromodel_wip/archive-date.html> at http://www.eda.org/ibis/macromodel_wip/archive-date.html
Mike
IBIS Macromodel Task Group
Meeting date: 18 February 2014
Members (asterisk for those attending):
Agilent: Fangyi Rao
Radek Biernacki
Altera: * David Banas
ANSYS: * Dan Dvorscak
Curtis Clark
Luis Armenta
Cadence Design Systems: * Ambrish Varma
* Brad Brim
Kumar Keshavan
Ken Willis
Ericsson: Anders Ekholm
Intel: * Michael Mirmak
Maxim Integrated Products: Hassan Rafat
Mentor Graphics: * John Angulo
* Arpad Muranyi
Micron Technology: Randy Wolff
* Justin Butterfield
QLogic Corp. James Zhou
Andy Joy
SiSoft: * Walter Katz
Todd Westerhoff
* Mike LaBonte
Teraspeed Consulting Group: Scott McMorrow
* Bob Ross
The meeting was led by Arpad Muranyi
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Opens:
- None
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Call for patent disclosure:
- None
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Review of ARs:
- Ambrish send updated backchannel BIRD to Mike for posting.
- Done
- Ambrish send clean backchannel BIRD to Michael M for open forum.
- Arpad not sure this was an AR from last week.
- Walter collect user statements regarding their packaging needs.
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New Discussion:
Package/interconnect modeling:
- Arpad: The required level of automation is an interesting question.
- Walter: I use the term "use model", which should be evaluated first.
- The sliding/swathing model was too complex, I did something simpler.
- I spoke with Randy about what he is prepared to deliver.
- Walter showed an example IBIS file:
- Arpad: Why does it have [Pin] RLC values?
- Walter: Only for tools that would not support the new format.
- [Pin Mapping] is useful for signal pins, to associate supply buses.
- This has two types of models Randy would like to use.
- One is for package pins, the other for the PDN.
- In the second example shown, all ports named VDD have the same voltage.
- The first example is an s56p.
- This connects every pin to every node.
- John: The declaration connects the port to a bus called VDD?
- Randy: That is correct.
- Walter: [Pin Mapping] is required for this.
- This example has just a few DQ/DQS pins, the real one would have a hundred.
- Scott McMorrow might ask to analyze this as a large s-param.
- Others might ask for something like swathing.
- This should be a straightforward model.
- Bob: This looks OK, but it must line up with the s-param ports.
- Walter: The tool generating this will have to take care of that.
- Bob: The Touchstone file will have to be checked.
- The name doesn't prove it has the right number of ports.
- Brad: It is good to walk before we run.
- Walter: The second example has one port per pin and per buffer supply node.
- This example has only power and ground for each buffer, no clamp ports.
- This has only power in it.
- Micron has indicated they need to deliver these separately.
- Arpad: The second example shorts all power pins on the same bus and the third
has them separate?
- Walter: Yes.
- Arpad: Do we need a rule that these would override [Pin Mapping]?
- Walter: There are some errors in my example.
- That rule is not needed.
- Arpad: The [Pin Mapping] shorts them together.
- Walter: We might need a keyword other than [Pin Mapping].
- Bob: That could be confusing.
- Walter: It knows how to connect buffer supply ports to the right supply nodes.
- John: We are considering models in which the PDN is not just simple shorts.
- It would be a conflict for the tool to implement [Pin Mapping] and the new
data as stated.
- We might have to say one overrides the other.
- Walter: An example further down shows die supply pad nodes being connected.
- We should support all of these use models.
- Bob: My reservation still stands, the parser must be able to check it.
- Walter: This may be beyond the scope of checking, like trying to verify that
an AMI DLL works.
- Arpad: We need to compare this to BIRDs 163 to 165.
- Walter: It would be best to see these examples in that syntax.
- My syntax has a Touchstone for each pin/buffer type, DQ, DQS, INPUT, etc.
by INPUT, I/O, etc.
- John: The EDA tools examine package models looking for one that applies?
- With multiple criteria more than one might satisfy.
- Users would have to disambiguate.
- Walter: There is a choice to be made, although the models should give nearly
the same results.
- At DesignCon I presented the precedence rules for this.
- Randy: Some software will allow certain overrides.
- Brad: Walter's proposal is similar to the precedence hierarchy we had before.
- John: The type syntax saves file space, there are always trade-offs.
- Walter: Model makers will choose the styles that are appropriate for users to
make decisions.
- Swathing is a separate discussion.
- Brad: That really is about coupled vs. uncoupled.
- Walter: A DDR4 bus would have about 130 pins, an s260p would be needed.
- Or we could have swathing.
AR: Arpad duplicate Walter's example using BIRDs 163-165
AR: Walter update new package model example with corrections and parameterized
length.
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Next meeting: 25 February 2014 12:00pm PT
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IBIS Interconnect SPICE Wish List:
1) Simulator directives
