[ibis-macro] Minutes from the 19 May 2009 ibis-atm-meeting

From: "Mike LaBonte (milabont)" <milabont@xxxxxxxxx>
To: "IBIS-ATM" <ibis-macro@xxxxxxxxxxxxx>
Date: Tue, 26 May 2009 14:49:17 -0400

Minutes from the 19 May 2009 ibis-atm-meeting are attached.

Mike

IBIS Macromodel Task Group

Meeting date: 19 May 2009

Members (asterisk for those attending):
  Adge Hawes, IBM
  Ambrish Varma, Cadence Design Systems
* Anders Ekholm, Ericsson
* Arpad Muranyi, Mentor Graphics Corp.
  Barry Katz, SiSoft
* Bob Ross, Teraspeed Consulting Group
  Brad Brim, Sigrity
  Brad Griffin, Cadence Design Systems
  Chris McGrath, Synopsys
  David Banas, Xilinx
  Deepak Ramaswany, Ansoft
  Donald Telian, consultant
  Doug White, Cisco Systems
  Eckhard Lenski, Nokia-Siemens Networks
  Essaid Bensoudane, ST Microelectronics
* Fangyi Rao, Agilent
  Ganesh Narayanaswamy, ST Micro
  Gang Kang, Sigrity
  Hemant Shah, Cadence Design Systems
  Ian Dodd, Agilent
  Jerry Chuang, Xilinx
  Joe Abler, IBM
* John Angulo, Mentor Graphics
  John Shields, Mentor Graphics
  Ken Willis, Cadence Design Systems
  Kumar Keshavan, Sigrity
  Lance Wang, Cadence Design Systems
  Luis Boluna, Cisco Systems
  Michael Mirmak, Intel Corp.
* Mike LaBonte, Cisco Systems
  Mike Steinberger, SiSoft
  Mustansir Fanaswalla, Xilinx
  Patrick O'Halloran, Tiburon Design Automation
  Paul Fernando, NCSU
  Pavani Jella, TI
  Radek Biernacki, Agilent (EESof)
* Randy Wolff, Micron Technology
  Ray Comeau, Cadence Design Systems
  Richard Mellitz, Intel
  Richard Ward, Texas Instruments
  Samuel Mertens, Ansoft
  Sam Chitwood, Sigrity
  Sanjeev Gupta, Agilent
  Shangli Wu, Cadence Design Systems
  Sid Singh, Extreme Networks
  Stephen Scearce, Cisco Systems
* Steve Pytel, Ansoft
  Syed Huq, Cisco Systems
  Syed Sadeghi, ST Micro
  Ted Mido, Synopsys
  Terry Jernberg, Cadence Design Systems
  Todd Westerhoff, SiSoft
  Vladimir Dmitriev-Zdorov
  Vikas Gupta, Xilinx
  Vuk Borich, Agilent
* Walter Katz, SiSoft
  Zhen Mu, Cadence Design Systems

------------------------------------------------------------------------
Opens:

--------------------------
Call for patent disclosure:

- No one declared a patent.

-------------
Review of ARs:

- Todd: Write IBIS s-param BIRD
  - Still working on it

- Arpad:  Write parameter passing syntax proposal (BIRD draft)
          for *-AMS models in IBIS that is consistent with the
          parameter passing syntax of the AMI models
          - TBD

- TBD:    Propose a parameter passing syntax for the SPICE
          - [External ...] also?
          - TBD

- Arpad:  Review the documentation (annotation) in the macro libraries.
          - Deferred until a demand arises or we have nothing else to do

-------------
New Discussion:

Continued review of IBIS-IS documents:

- Walter has not received the remaining documents from Synopsys.
  - He will call

Walter showed a new boiler-plate section:
- The title is "IBIS Interconnect SPICE Subckts"
- Arpad: It is now accepted that * comments can have content ahead of them
  - Bob: We should stick to the rigid rule
    - * is at the beginning of a line, $ can be after
    - If HSPICE has a secret enhancement we don't have to use it
  - Arpad: These files may appear, and tools would have trouble with them
  - Walter: Concur with Bob
- Walter added .INCLUDE
- John: Should we support .ALTER?
  - Arpad: No we are not supporting control statements
- Arpad: There are rules for automatic INCLUDE for SEARCH path files
  - Walter: Only EDA tools should "own" search path capabilities
- INCLUDE assumes relative paths are relative to current file
  - Arpad: Does relative mean relative to top level file?
- Mike L: Should we allow only simple file names, no path?
  - Walter: Sometimes it is convenient to organize into directories
    - EDA tools can use their own search path mechanisms
  - Mike L: It works well when tools combine simple file names with a search 
mechanism

Walter showed the built-in functions list:
- Arpad: Should we eliminate non-linear functions?
  - Walter: These are in parameters, and evaluate to constants

Walter showed the SUBCKT page:
- Some simulators require a SUBCKT name after .ENDS
  - Arpad: Older simulators did not allow nesting
- Mike L: It adds no information, is just for checking
- Walter: We should specify nesting in the scoping rules
- Arpad: Do we require include files to have balanced subckt/ends?
  - Walter: Yes
- Walter made a notation that scoping rules need work

Walter showed node naming pages:
- Walter: It would be best not to have dotted hierarchical node names
  - Mike L: Agree, these can cause trouble
- Arpad: GROUND should be accepted as well as GND
- Arpad: Are we sure we do not want dotted hierarchical node names?
  - Mike L: Maybe, but only if they are relative to the current SUBCKT
  - Arpad: They can be useful for probing subckt voltages
    - Also for .CONNECTing nodes in different circuits
  - Walter: Do we allow them on the .SUBCKT line?
    - Arpad: No
    - Mike L: These are terminal definitions, not node calls

Walter briefly showed R, C, L, K, T, S, and EFGH pages
- There were few comments, we already covered those pages

Arpad: How do we proceed?
- Mike L: We need the remaining documents from Synopsys
- Walter: Will contact them again

AR: Walter contact Synopsys about remaining documents

Arpad thanked Walter for his work on these documents

Next meeting: 26 May 2009 12:00pm PT

--------

IBIS Interconnect SPICE Wish List:

1) Simulator directives

[ibis-macro] Minutes from the 19 May 2009 ibis-atm-meeting

Other related posts: