[ibis-macro] Minutes from the 24 jun 2008 ibis-atm meeting
- From: "Mike LaBonte (milabont)" <milabont@xxxxxxxxx>
- To: "IBIS-ATM" <ibis-macro@xxxxxxxxxxxxx>
- Date: Wed, 25 Jun 2008 14:02:29 -0400
Minutes from the 24 jun 2008 ibis-atm meeting are attached. ARs:
AR: Walter send example of "Framis" model definition
AR: Arpad send pointer to AMS examples
Mike
IBIS Macromodel Task Group
Meeting date: 24 Jun 2008
Members (asterisk for those attending):
Ambrish Varma, Cadence Design Systems
Anders Ekholm, Ericsson
* Arpad Muranyi, Mentor Graphics Corp.
Barry Katz, SiSoft
* Bob Ross, Teraspeed Consulting Group
* Brad Brim, Sigrity
Brad Griffin, Cadence Design Systems
David Banas, Xilinx
Donald Telian, consultant
Doug White, Cisco Systems
Essaid Bensoudane, ST Microelectronics
Fangyi Rao, ???
Ganesh Narayanaswamy, ST Micro
Gang Kang, Sigrity
Hemant Shah, Cadence Design Systems
* Ian Dodd, Agilent
Joe Abler, IBM
* John Angulo, Mentor Graphics
John Shields, Mentor Graphics
Ken Willis, Cadence Design Systems
Kumar
Lance Wang, Cadence Design Systems
Luis Boluna, Cisco Systems
* Michael Mirmak, Intel Corp.
* Mike LaBonte, Cisco Systems
Mike Steinberger, SiSoft
Mustansir Fanaswalla, Xilinx
Patrick O'Halloran, Tiburon Design Automation
Paul Fernando, NCSU
Radek Biernacki, Agilent (EESof)
* Randy Wolff, Micron Technology
Ray Comeau, Cadence Design Systems
Richard Mellitz, Intel
Richard Ward, Texas Instruments
* Sam Chitwood, Sigrity
Sanjeev Gupta, Agilent
Shangli Wu, Cadence Design Systems
* Sid Singh, Extreme Networks
Stephen Scearce, Cisco Systems
Steve Pytel, Ansoft
Syed Huq, Cisco Systems
Syed Sadeghi, ST Micro
Terry Jernberg, Cadence Design Systems
Todd Westerhoff, SiSoft
Vikas Gupta, Xilinx
Vuk Borich, Agilent
* Walter Katz, SiSoft
Zhen Mu, Cadence Design Systems
--------------------------
Call for patent disclosure:
- No one declared a patent.
-----
Opens:
- Arpad: Would like to continue the recent email discussion here
- Bob: There is a potential BIRD on AMI for clarification
- Change 6C title to "Algorithmic Modeling Interface (AMI)"
- Will be proposed at IBIS Open forum
- Michael M: Holidays are coming, should we reschedule the next meeting?
- No one registered any date conflicts
- Weekly meetings will continue for now
-------------
Review of ARs:
- Walter send presentation to Mike
- Done
- Mike post Walter's presentation
- Done
- Arpad send email to solicit feedback on "Interconnect-only, LTI SPICE"
- Done
- David Banas report Xilinx position on LTI assumption for SerDes
- No update
- Arpad: Write parameter passing syntax proposal (BIRD draft)
for *-AMS models in IBIS that is consistent with the
parameter passing syntax of the AMI models
- TBD
- TBD: Propose a parameter passing syntax for the SPICE
- [External ...] also?
- TBD
- Arpad: Review the documentation (annotation) in the macro libraries.
- Deferred until a demand arises or we have nothing else to do
-------------
New Discussion:
Walter showed a presentation "Electrical Module Description EMD Review":
- Slide 5: Subckt Views are different models for the same thing
- One may be for higher frequency, for example
Arpad brought up the "Question on setting the EMD direction" emails:
- We want to get expert feedback to avoid making mistakes.
- Brad: the language we use may be important
- We may have to call it "SPICE-like", not SPICE
- Ian: How about calling it a "nodal netlist"?
- Michael M: We have to avoid "mission creep"
- 3 needs have been identified:
- Netlist to connect components
- Wrappers for standardized blocks
- Modeling of interconnect
- May need to model new elements in the future
- Walter: We can add new elements with BIRDs
- Michael M: It has to be clear that what we define has to be extensible
- It is difficult to separate "what" from "how"
- Arpad: Once we start modeling blocks, we tend to go toward AMS
- Michael M: SPICE is cheap, AMS is expensive
- Arpad: Walter's example circuit looks like AMS
- Walter: Anyone should be able to translate this to any simulator.
- Ian: AMS languages are standard, why not use that?
- Walter: It would be better to be neutral
- Michael M: We agree on the netlist part
- The difficult part is describing what is inside the boxes
- There is no RLGC in Verilog-A
- Walter: We can use ICM RLGC files (S-param too)
- Michael M: We have to avoid saying it is like SPICE but not define it
- Arpad: It would be easy to use AMS
- Michael M: We can't punt by pointing to another specification
- We have to completely specify our language
- Arpad showed the VAMS syntax to call the IBIS_R element
- Walter: There are many formats; this is one
- Walter: We need to focus on what models to have, not netlist format
- Bob: Is LTI really what we mean?
- Active circuits can be LTI, too
- Walter: This is only about passive interconnect
- Ian: we might have a temperature dependent resistor
- Walter: the R value is calculated, but does not change during simulation
- Ian: Adaption of a link to temperature has to be modeled
- Walter: that does not have to be modeled "at speed"
- Arpad: Can we rule out F elements?
- Brad: Some tools convert S-params to controlled sources & LaPlace elements
- RLGC models don't have enough bandwidth
- Mike L: Controlled sources with equations may be needed
- Arpad: The equations will be evaluated before simulation.
- Michael M: We are now discussion the "how"
- Walter added Controlled Sources to the element list in the presentation
- Sam: DC votages are useful for shorting nodes together
- How about a 0 ohm resistor?
- The best choice depends on the simulator
- How about a "short"?
Michael M: We need to discuss how to add new elements
- Walter: Will define a "Framis" element example, sent by email
- Brad: Would like a pointer to AMS formats
- Arpad: It's in the old macromodel files
AR: Walter send example of "Framis" model definition
AR: Arpad send pointer to AMS examples
Next meeting: 01 Jun 2008 12:00pm PT
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