Minutes from the 26 January ibis-atm meeting are attached.
The following document, which was discussed during the meeting, has been
posted to the work archive.
*DATE* AUTHOR <http://ibis.org/macromodel_wip/archive-author.html>
ORGANIZATION <http://ibis.org/macromodel_wip/archive-org.html> TITLE
<http://ibis.org/macromodel_wip/archive-title.html> FORMATS
26-JAN-2016 Walter Katz SiSoft DUT vs DIA (zip
<http://ibis.org/macromodel_wip/archive/20160126/walterkatz/DUT_vs_DIA.zip>
)(pptx
<http://ibis.org/macromodel_wip/archive/20160126/walterkatz/DUT%20vs%20DIA/ReferenceNode.pptx>
)
IBIS Macromodel Task Group
Meeting date: 26 January 2016
Members (asterisk for those attending):
ANSYS: * Dan Dvorscak
* Curtis Clark
Avago (LSI): Xingdong Dai
* Bob Miller
Cadence Design Systems: * Ambrish Varma
Brad Brim
Kumar Keshavan
Ken Willis
Cisco: Seungyong (Brian) Baek
eASIC: David Banas
Marc Kowalski
Ericsson: Anders Ekholm
GlobalFoundries: Steve Parker
Intel: Michael Mirmak
Keysight Technologies: Fangyi Rao
* Radek Biernacki
Maxim Integrated Products: Hassan Rafat
Mentor Graphics: John Angulo
* Arpad Muranyi
Micron Technology: Randy Wolff
Justin Butterfield
QLogic Corp.: James Zhou
Andy Joy
SiSoft: * Walter Katz
Todd Westerhoff
Mike LaBonte
Synopsys: Rita Horner
Teraspeed Consulting Group: Scott McMorrow
Teraspeed Labs: * Bob Ross
TI: Alfred Chong
The meeting was led by Arpad Muranyi.
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Opens:
- None.
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Call for patent disclosure:
- None.
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Review of ARs:
- None.
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Review of Meeting Minutes:
- Arpad: Does anyone have any comments or corrections? [none]
- Arpad: Motion to approve the minutes.
- Ambrish: Second.
- Arpad: Anyone opposed? [none]
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New Discussion:
Back Channel BIRD 147.1:
- Discussion: Arpad asked if Ambrish had made progress in this area. Ambrish
said that he had noted a lot of interest and positive feedback at DesignCon.
He said he planned to restart work on the topic shortly. Arpad asked Walter
whether he had any plans to submit his own optimization proposal, in light of
SiSoft's recently announced optimization tool. Walter said that they were
interested in co-optimizing Tx and Rx models, but their tools had thus far
introduced techniques that worked with standard AMI Models, and thus were
independent of this topic. He also noted that he had produced a proposal that
allowed Tx and Rx models to advertise their capabilities and communicate.
That proposal had been tabled until Cadence had a chance to respond. Bob M.
noted that Avago had a lot of interest in getting Tx to Rx communication for
co-optimization because they wanted a technique that would allow them to match
what is done in the actual hardware. There was some discussion on how easy
it
would be for people to find the latest working versions of the BIRDs and
proposals. Radek suggested that Ambrish check for the latest version of his
proposal and make sure it is posted. Walter said he would do the same for his
proposal.
Discussion of language corrections regarding "ground":
- Walter: [Sharing the "Device Under Test vs. Device In Action presentation
he had sent to the ATM group mailing list].
- [referring to slide 2, which shows Figure 16 from the IBIS 6.1 spec]
- Aside from AMI, [External Model], and perhaps some packaging information,
IBIS is generally a specification for how to generate a behavioral model of
a device from measurements.
- This figure shows the test fixture for doing the measurements.
- In this case, we are measuring the voltage at the Pin in a test fixture.
- Every measurement has a reference, which is the reference for the test
fixture, which is shown by the ground symbol.
- For a classic IBIS model that has only the [Voltage Range] keyword, the
assumption is that the reference for that Model is a ground Pin.
From the spec, "For many buffers, only one power pin and one common ground
pin terminal are used."
- That terminology isn't very clear ("common ground pin terminal"). [Pin
Mapping] actually tells you which GND [Pin] is the reference ground for the
[Model].
- The standard says to hook the test fixture probe to the I/O pin and make
sure the test fixture is grounded to the appropriate GND [Pin] of that
device. They call that ground the "absolute ground" or the "absolute ground
Pin."
- That's the reference for the V_fixture voltage and the package model.
- [referring to the next slide "Device in Action"]
- Same buffer now "in action."
- DUT is now a device in action (DIA).
- We really now have a 3 terminal device, I/O Pad, VDD, VSS.
- We don't know what VDD and VSS are at any given time, they are now provided
by a PDN.
- There is no "absolute ground" here. There is VSS, which is connected to the
GND Pin for this buffer.
- We actually only have two voltage differences.
- IBIS only talks about a DUT.
- The paragraph before figure 16 is confusing.
- Attempt to clarify that with proposed new language:
- "For [Model]s that do not specify [Pulldown Reference] or [GND Clamp
Reference] the reference for the V_fixture voltage shall be a ground pin
for that [Model] under test as specified in the [Pin Mapping] section or
a common ground pin."
- C_comp would also be connected to this.
- When [Pulldown Reference] or [GND Clamp Reference] are specified, and they
are non-zero, then we need to create a reference node for that device.
- If you're measuring V_fixture, it has to be with respect to some reference
node.
- We could define a reference node with a resistor to either the [Pullup
Reference] or [POWER Clamp Reference], and a resistor to either the
[Pulldown Reference] or [GND Clamp Reference]. Create a voltage divider
between the existing reference nodes.
- Introduce 4 new parameters to define these resistance values.
- You would also know where to connect C_comp based on which of the new
parameters R_DUT_pdref or R_DUT_gcref is used.
- We need a reference node when the device is in action.
- We can't rely on the rails providing what the [Model] says. We assume they
come from a PDN and can vary.
- We need a reference node within the device, so when the device is in action
we can compare the voltage at the pad relative to that node with threshold
values like Vinl, Vinh.
- None of these other references ([Pullup Reference], etc.) make any sense
unless we have a reference node inside the device in action.
- Bob R: I don't think we need to complicate this section.
- With respect to extracting IBIS parameters, the external reference is
already defined as ground for all voltages.
- We already have a way to define V_fixture with respect to an external
reference voltage, which need not be any of the rails. That is supported
and can be used to generate the internal K table models.
- We have a more general solution now without the additional parameters.
- This proposal also introduces the notion that we are extracting the [Model]
from the Pin interface. The extracted model is at the die. There would
have to be a de-embedding if we were hooking up to a ground pin to power
the device during measurement. I don't think that was intended. I think we
can safely assume the references are rock solid, at least for SPICE
extraction.
- In general, I want five voltages pu, pc, pd, gc, pad. We shouldn't try
to simplify this figure.
- Discussion: Radek said he thought Walter's proposal was a step in the right
direction. He said that for extraction, even if all the references are
different from zero they are with respect to some local ground. That node
exists and needs to be pointed out as Walter was attempting to do. He said
we therefore need six nodes, not five. Arpad agreed and wondered if we might
introduce an Int_ref similar to Ext_ref. Both felt the proposed bridge
divider circuit for generating the reference node might be too limiting.
Radek wondered if it wouldn't be easier to leave that to the package model
maker so we didn't have to invent a bridge circuit interpretation. Bob
pointed out that we have an inherent conflict with some measurements based
on the die and some based on the Pin. Radek agreed and said we would need to
revisit the topic.
- Arpad: Thank you all for joining.
AR: Ambrish to find and post the latest version of his Back Channel proposal.
AR: Walter to find and post the latest version of his co-optimization proposal.
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Next meeting: 2 February 2016 12:00pm PT
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IBIS Interconnect SPICE Wish List:
1) Simulator directives
