Minutes from the April 26, 2016 IBIS-ATM meeting are attached. The [Pin
Reference] BIRD draft 1 document presented by Walter Katz is linked below.
DATE
AUTHOR<http://ibis.org/macromodel_wip/archive-author.html>
ORGANIZATION<http://ibis.org/macromodel_wip/archive-org.html>
TITLE<http://ibis.org/macromodel_wip/archive-title.html>
FORMATS
26-APR-2016
Walter Katz
SiSoft
Pin Reference BIRD draft 1
(zip<http://ibis.org/macromodel_wip/archive/20160426/walterkatz/Pin_Reference_BIRD_draft_1.zip>)(docx<http://ibis.org/macromodel_wip/archive/20160426/walterkatz/Pin%20Reference%20BIRD%20draft%201/Pin_Reference.docx>)
Randy Wolff
IBIS Macromodel Task Group
Meeting date: 26 April 2016
Members (asterisk for those attending):
ANSYS: * Dan Dvorscak
Curtis Clark
Broadcom (Avago): Xingdong Dai
Bob Miller
Cadence Design Systems: Ambrish Varma
Brad Brim
Kumar Keshavan
Ken Willis
Cisco: Seungyong (Brian) Baek
eASIC: David Banas
Marc Kowalski
Ericsson: Anders Ekholm
GlobalFoundries: Steve Parker
Intel: * Michael Mirmak
Keysight Technologies: Fangyi Rao
Radek Biernacki
* Ming Yan
Maxim Integrated Products: Hassan Rafat
Mentor Graphics: John Angulo
* Arpad Muranyi
Micron Technology: * Randy Wolff
Justin Butterfield
QLogic Corp.: James Zhou
Andy Joy
SiSoft: * Walter Katz
Todd Westerhoff
* Mike LaBonte
Synopsys: Rita Horner
Teraspeed Consulting Group: Scott McMorrow
Teraspeed Labs: * Bob Ross
TI: Alfred Chong
The meeting was led by Arpad Muranyi.
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Opens:
- Randy Wolff took minutes for the meeting.
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Review of ARs:
- Ambrish to check for a collaborator's feedback on his nearly ready new
version of the Backchannel proposal.
- No update.
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Call for patent disclosure:
- None.
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Review of Meeting Minutes:
- Arpad: No minutes were sent out for the last meeting.
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New Discussion:
Bob Ross moved to table item #9 "How to handle missing min/max data". Dan
Dvorscak seconded the motion. There were no objections.
[Pin Reference] BIRD draft:
Walter noted when a device in action does not have stable rail voltages, the
DUT had a reference of the test fixture ground, but for a DIA we don't know
where the reference is. For every pin on a device we can specify for each
signal name what its reference is. The meaning of that for power or ground
pins is not clear. It it useful for I/O buffer pins so one knows the
reference for the DIA for measurements. A new section [Pin Reference] lists a
pin_name and a signal_name. If there is no [Pin Reference] section (or other
qualifiers listed in the BIRD), the EDA tool must choose a reference node for
simulation. EDA tools do this at least two different ways. This may be the
biggest technical issue to resolve. For measurements at the I/O pin relative
to the simulator reference node, the voltage at the I/O pin is adjusted.
Bob asked do you shift the simulation voltage or the reference voltage?
Walter stated that you can shift the measurement levels like Vinl or the
reference voltage. Shifting Vinl dynamically is difficult, and it is easier
to shift the waveform voltage relative to the reference voltage.
Walter stated that the Vth correction in affect applies to the difference
between the actual voltage at the power rail minus the voltage at the ground
rail. The example shown is one Bob came up with for PECL and ECL. Walter
noted that VEE for ECL is always the reference voltage. This rail (0V) is
less sensitive than the power rail.
Walter noted this keyword does not apply to the DUT. If the model maker
doesn't like the assumption of the ground clamp reference as the reference, he
can specify another rail as the reference using this keyword.
Bob that in Pin 2 of the model example, he may have made a mistake. For PECL,
the 5.0V rail should be the [Pin Reference]. That is the dominant rail for
reference for thresholds. Without [Pin Mapping] we don't know the reference
pin for simulation. Walter noted that [Pin Mapping] is required if you want
to use [Pin Reference]. Bob added that shifting the output voltage at the I/O
pin solves a lot of problems. You get the actual simulation waveform
displayed, but another waveform could be stored away looking for crossing
points for measurements. Walter plots the waveform relative to the local
reference node. There is the waveform the buffer sees relative to its
reference and the waveform the simulator sees relative to the simulator
reference. Bob noted that bus labels might be used with this too. If there
is a ground reference shift, with all rails shifted relative to ground, for
PECL could apply -3V and 2V rails. There is a global ground and a rail
relative to that for a DIA. He can show an example of PECL and other open
source topologies where the most dominant positive rail is the reference.
Walter noted that one thing to look at is how Vinl changes with respect to
what rail. Vth for receiver thresholds may adjust based on the power clamp
reference, but the waveform voltage may adjust relative to the ground clamp
reference.
Bob asked should this be only for receiver specifications, because timing test
load specs are taken off of the setups documented in the datasheet. Walter
said that everything in the datasheet assumes ground is ground as in the
reference voltage. Bob said that, however, the timing test load Vmeas and
Vref is a fixed setup and should be done ahead of timing to simulate relative
delays to the test load.
Walter noted that Radek is not present, and he understands a lot of these
issues. We need to get his comments. Walter noted that we should proceed
knowing that this BIRD will get approved, with some editorial work. The
interconnect and editorial groups should proceed assuming this BIRD will get
approved. Power aware simulations, receiver thresholds, and [ISSO *] are the
only sections needing more discussion, but the editorial group's work should
be able to proceed faster with this BIRD. Bob noted he thinks the BIRD needs
to be fully vetted, and what version of IBIS it goes into such as 6.2 or 7.0
needs to be decided. Arpad responded that this BIRD may be needed to help
with the ground cleanup for IBIS 6.2. Mike LaBonte noted he could work with
Bob offline to make sure the BIRD fully supports PECL.
Arpad asked Michael what he thought about the proposal. Michael said it is
worth considering. He didn't think, per Walter's point, that it conflicts
with the interconnect draft.
Walter noted he will be travelling to SPI and will miss several meetings. He
will read meeting minutes and respond by email.
Bob noted that we should minimize forward references in the BIRD draft.
Arpad asked if we will get an updated version before Walter travels. Walter
noted that he didn't have an update planned. Mike noted that he will be
reviewing it and will offer comments if he has any.
Mike moved to adjourn. Dan Dvorscak seconded. The meeting adjourned.
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Next meeting: 3 May 2016 12:00pm PT
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IBIS Interconnect SPICE Wish List:
1) Simulator directives
