[ibis-macro] Setting up of an inout pin to valid logic state

From: Chetan Kumar <Chetan.Kumar@xxxxxxx>
To: "ibis-macro@xxxxxxxxxxxxx" <ibis-macro@xxxxxxxxxxxxx>
Date: Mon, 10 Mar 2014 05:48:33 +0000

Hi Experts,

I have a typical problem here to generate the IBIS model for a full chip 
database. I have the OA database and netlist of entire chip. There are two pins 
P0 and P1 which are inout and I am supposed to model them. The pins P0 and P1 
can be set to logic 0 or 1 using a vector bits of input pins. I need to drive a 
vector on SDA pin to put this P0/P1 to logic 1 or 0. Due to completities of the 
chip, it takes me 8 hours of simulation time before P0/P1 goes to 0 or 1. Is 
there any other way by which we can get the I-V V-t data for P0/P1.

Thanks and Best Regards,
Chethan

[ibis-macro] Setting up of an inout pin to valid logic state

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