[ibis-macro] Today's version of the library
- From: "Muranyi, Arpad" <arpad.muranyi@xxxxxxxxx>
- To: <ibis-macro@xxxxxxxxxxxxx>
- Date: Fri, 30 Sep 2005 13:39:32 -0700
Hello everyone,
Here is today's version of the building block library.
I hope the attachments will make it through the reflector,
but if not I will find another way to get it to you.
The biggest change in this version is the IBIS_IO module.
I implemented it so that this will not have to be copied
for every instance (as we feared before), but the IV and
VT tables are passed into it as array parameters. This
would make it kind of ugly on the calling statement, but
there is a workaround for that too by using the `include
and `define statements. To illustrate this, I am attaching
a file called "LibNet.va" which is the equivalent of what
will be macro model templates calling the building blocks
from the library. (I am using this file to test my library
modules). If you scroll to the bottom, you will see two
ways of calling the IBIS_IO module, the first is the
ugly way (without any `includes and `defines), and the
second is the nicer way. The second syntax will use the
data files also included in the attachment of this email.
These data files represent four (4) types of an IO buffer,
one without ODT, another with ODT to GND, the 3rd with
an ODT to Vcc and the last with a dual ODT to Vcc and GND.
If nothing is passed into the IBIS_IO module, it will just
use its own default parameters, and will still work. Note
that these data files contain bare minimum tables, just for
illustration purposes.
Lastly, I am including an HSPICE .sp file called LibTest.sp,
which calls the LibNet.va file and a B-element, which uses
the (also included) IBIS file called "test_ams.ibs". This
IBIS file contains the same buffer model data that I
described above, and the B-element will use it. This file
can be used to generate a waveform overlay of the Verilog-A
and the HSPICE B-element results. Note that you must have
the latest release of HSPICE (2005.09) for this to work.
The way these files should be "installed" is as follows:
Put the .SP and the .IBS files in a directory where you will
run the HSPICE simulations. Create a subdirectory in it
called AMS_files and unzip the content of the .ZIP file
into that. You may have to fix some of the path statements,
but this should work.
Note that the "IBIS_macro_library.va" file in the .ZIP file
is the same as the one called "IBIS_macro_library_2005_09_30.va".
I am just stamping them with dates for backup and safekeeping
purposes while I am working on the file without the date in it.
Comments:
=========
I had to comment out the controlled capacitor and inductor
models in the library, because HSPICE complained about my
syntax. I will look into this and fix it ASAP.
The IBIS_IO module has a few lines which hard code some
array lengths (search for 3016 if you want to find it).
The three lines above this supposed to work the way I
understand the Verilog-A LRM, but it is either not
implemented in HSPICE or is a bug or misinterpretation
of the LRM. I am working on this with the Synopsys guys.
HSPICE also doesn't like the array parameters, and will
issue a message saying that it is ignoring them:
"hsp-vacomp: Ignoring param modification info for 'I_pc'."
If I pass the VT data HSPICE will crash. I think they didn't
implement array parameter passing yet, and I am working on
this one with them too.
So here we are with an almost working solution. Hopefully
by the time this library will be widely used, HSPICE will
have these issues fixed. It would be nice if people on
this list could try it in other tools that support Verilog-A
to see those tools will do with this library...
Please give me your feedback so I can improve on this. I
am most specifically curious what you think about the calling
mechanism of the IBIS_IO module. My plan is to continue with
this style, and make other versions of this IO model (INPUT,
OUTPUT, OPEN_xxx, etc). I don't want to duplicate this style
and then have to change them each...
Also, I am thinking of using the same style for our yet to
be written PWL sources, as far as passing the data tables
into them. Any thought on that?
So much for now. Have a nice weekend, and have fun with
this new library.
Arpad
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