[ibis-macro] Two issues brought up in today's meeting - Test Points and Bus switches
- From: "Walter Katz" <wkatz@xxxxxxxxxx>
- To: "IBIS-ATM" <ibis-macro@xxxxxxxxxxxxx>
- Date: Tue, 19 Aug 2008 18:13:33 -0400
All,
Two issues brought up in today's meeting - Test Points and Bus switches. The
following shows how these would be implemented in EMD.
Walter
Test Points
Consider the following emd file consisting of a backplane and one connection
between pin 1 of two connectors (J1 and J2). Also assume there is a test
point on the net (DATA). The test points get exposed as external pins, and
can be optionally used in views that support the test point node. Typically
s-parameter models would normally not expose these test points.
[Module] Simple_Backplane
[mPin]
J1.1
TP.1
J2.2
[Extended Nets]
DATA J1.1 J2.1 TP1.1
[View] wline Hspice 3GHz
DATA J1.1 J2.1 TP1.1 file= DATA_wline.mod subckt=DATA
[View] sparam Hspice 20GHz
DATA J1.1 J2.1 file= DATA_sparam.mod subckt=DATA
The wline view exposes TP1.1 in addition to J1.1 and J2.1
The sparam view is a single Touchstone file between J1.1 and J2.1, it does
not expose TP1.1
Bus switches
This can be done in two different ways.
Tx.1 is an output pin that goes to the input of a bus (or mux) switch
(BUS.1)
The outputs of BUS are BUS.2 and BUS.3.
First way is to create two extended nets, and include the bus switch model
as a subckt inside the interconnect
[Module] Bus_switch
[mPin]
Tx.1
Rx1.1
Rx2.1
[Extended Nets]
DATA1 Tx.1 Rx1.1
DATA2 Tx.1 Rx2.1
[View] wline Hspice 3GHz
DATA1 Tx.1 Rx1.1 file= DATA.mod subckt=DATA1
DATA2 Tx.1 Rx2.1 file= DATA.mod subckt=DATA2
DATA.mod
.subckt DATA1 Tx Rx
w1 Tx 0 bus_1 0 N=1 RLGCmodel=wline L=.1
xbus bus_in bus_out bus
.include bus.mod
w2 bus_out 0 Rx bus 0 RLGCmodel=wline L=.2
.ends DATA1
*
.subckt DATA2 Tx Rx
w1 Tx 0 bus_1 0 N=1 RLGCmodel=wline L=.1
xbus bus_in bus_out bus
.include bus.mod
w2 bus_out 0 Rx bus 0 RLGCmodel=wline L=.3
.ends DATA2
Second way is to create three extended (electrical) nets, and use an IBIS
bus switch model (not supported today in IBIS). The EDA tool would determine
that BUS1 is a bus or mux (either by using an enhanced IBIS file, or a EDA
private library that understood bus switches). The EDA tool would generate
the two electrical/extended nets, inserting the appropriate bus model.
[Module] Bus_switch
[mPin]
Tx.1
Rx1.1
Rx2.1
[Components]
BUS1 bus.ibs component=bus
[Extended Nets]
Tx Tx.1 BUS1.1
DATA1 BUS1.2 Rx1.1
DATA2 BUS1.3 Rx2.1
[View] wline Hspice 3GHz
Tx Tx.1 BUS1.1 file= DATA.mod subckt=Tx
DATA1 BUS1.2 Rx1.1 file= DATA.mod subckt=DATA1
DATA2 BUS1.3 Rx2.1 file= DATA.mod subckt=DATA2
DATA.mod
.subckt Tx Tx Bus
w1 Tx 0 Bus 0 RLGCmodel=wline L=.1
.ends Tx
*
.subckt DATA1 Bus Rx
w2 Bus 0 Rx 0 RLGCmodel=wline L=.2
.ends DATA1
*
.subckt DATA2 Bus Rx
w2 Bus 0 Rx 0 RLGCmodel=wline L=.3
.ends DATA2
Other related posts:
- » [ibis-macro] Two issues brought up in today's meeting - Test Points and Bus switches
