[ibis-macro] VinL, VinH, Data Derivation, Test Fixture Ground, Absolute Ground, ...

From: Walter Katz <wkatz@xxxxxxxxxx>
To: "IBIS-ATM" <ibis-macro@xxxxxxxxxxxxx>
Date: Fri, 15 Jan 2016 23:45:22 -0500 (EST)

All,

There seems to be some controversy of the reference node that needs to be
used in conjunction with IBIS Model levels such as VinL and VinH. One of
the sources of confusion is how to setup a Device Under Test (DUT). I
believe that one of the rail voltages connected to the buffer must be the
reference node, and generally this is either the pulldown rail or ground
clamp rail terminal of the buffer (what IBIS calls the common ground pin
terminal). In several places in IBIS (see for example page 72 of IBIS 6.1,
see below). I think the first paragraph should have been:

Figure 16 illustrates a general configuration from which a [Rising
Waveform] or [Falling Waveform] is extracted. The DUT die shows all of the
available power and ground pin reference voltage terminals. For many
buffers, only one power pin and one common ground pin terminal are used.
The absolute GND common ground pin is the reference for the V_fixture
voltage and the package model equivalent network. It can also serve as a
reference for C_comp, unless C_comp is optionally split into component
attached to the other reference voltages.

The picture should use "GND" or "VSS" instead of the Earth Ground Symbol
(as it was when the IBIS spec did not have graphics).

For Test Fixture voltage measurements to make any sense, they must be
referenced to the common ground pin terminal. In any event, absolute
ground here only refers to the Test Fixture reference. Concluding from
this description of how to hook up a test fixture to the statement that
all simulation waveform measurements when the common ground pin is hooked
up to a floating ground requires that the EDA tool evaluates the waveform
of the I/O pin referenced to the common ground pin terminal. Note that
IBIS can choose Si_location and Timing_location at the Pin or Die. If
these locations are at the Die, then the I/O waveform must be reference to
the common ground die terminal.

Page 72

Figure 16 illustrates a general configuration from which a [Rising
Waveform] or [Falling Waveform] is extracted. The DUT die shows all of the
available power and ground pin reference voltage terminals. For many
buffers, only one power pin and one common ground pin terminal are used.
The absolute GND is the reference for the V_fixture voltage and the
package model equivalent network. It can also serve as a reference for
C_comp, unless C_comp is optionally split into component attached to the
other reference voltages.

The [Composite Current] I-T table includes all of the current through the
[Pullup Reference] terminal. If the [POWER Clamp Reference] terminal is
the same as the [Pullup Reference] terminal (according to the [Pin
Mapping] keyword table), the [Composite Current] entries include the
currents through both the [POWER Clamp] and [Pullup] sections of the DUT
(for example, when an on-die terminator is connected to the power
reference terminal). Note that the terminals are shown in terms of
separately defined reference voltages, but still exist even if they are
defined with default [Voltage Range] or 0 V settings.

Figure 1- [External Reference] - (used only for non-driver modes)

Walter Katz

<mailto:wkatz@xxxxxxxxxx> wkatz@xxxxxxxxxx

Phone 303.449-2308

Mobile 303.335-6156

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[ibis-macro] VinL, VinH, Data Derivation, Test Fixture Ground, Absolute Ground, ...

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