All,
I now understand why referencing has been such a hard thing to explain and
understand, because there are many "references", and they mean different
things to many people.
First, we need to agree that the BEHAVIOR of a buffer only depends on the
relative voltages at all of its terminasls (and the currents and things
connected to the terminals).
Now let's talk about what these relative voltage mean starting with a
simple case of an Input, with a Power_clamp_ref, Gnd_clamp_ref and an I/O
terminal. The three voltages that one can measure are:
V(I/O, Gnd_clamp_ref), V(Power_clamp_ref, Gnd_clamp_ref),
V(Power_clamp_ref ,I/O Gnd_clamp_ref), which have the obvious constraint
that:
V(Power_clamp_ref, Gnd_clamp_ref) = V(I/O, Gnd_clamp_ref)+
V(Power_clamp_ref ,I/O Gnd_clamp_ref)
There are lots of [Model] subparameters that are defined in a [Model] that
are used for timing and silicon protection. Subparameter are often
sensitive to just one of these three voltage measurements. For example,
Overshoot_low might be sensitive to V(I/O, Gnd_clamp_ref), while
Overshoot_low might be sensitive to V(Power_clamp_ref ,I/O Gnd_clamp_ref),
while Vinl and Vinh might be sensitive to .5*V(Power_clamp_ref,
Gnd_clamp_ref). These sensitivities are likely different for CMOS, TTL,
ECL, PECL.
But ultimately, there is a metal path from the die to the pin, and then
from the pin to another component on the board, a finally from that pin to
another die. In the package the path from die to pin is likely referenced
to plane connected to the Gnd_clamp_ref for CMOS, and then on the PCB to
the other component. Both components should have a pin connected to their
respective Gnd_clamp_ref and both of these pins should be connected to a
PCB plane net (e.g. GND, VSS, .).
But what if a component is PECL and the Gnd_clamp_ref=-2.5V and the
Power_clamp_ref=+2.5V relative to a true GND plane net on the PCB. There
is a connection on the PCB between this pin and a I/O pin on another
component which has a similar Gnd_clamp_ref=-2.5V and
Power_clamp_ref=+2.5V. This connection on the PCB should reference a plane
net that is either the +2.5V rail, or the -2.5V rail, and the rail chosen
on the PCB should be the same plane rail that was used as the plane below
the trace in the package.
Again, as EDA Vendors we do not need to know which of these rails the
interconnect in the package references, only the model maker needs to know
that information when he instantiates W lines in the subckt, but to be
electrically legal, the interconnect in the package must reference a
signal_name on one of the components POWER or GND pins. It is the
responsibility of the PCB Layout Designer to make sure the connections to
the I/O pin on the PCB are referenced to planes connected to the same
POWER or GND pins. Note that this is totally independent of which of the
three terminal to terminal measurements are used as a reference for the
measurement thresholds.
The data book should indicate for each I/O pin which POWER or GND
signal_name in the package the PCB designer should use as the reference
plane for connections to each of the I/O pins in a component. I think this
is by default the "Ground" pins.
Walter
Walter Katz
<mailto:wkatz@xxxxxxxxxx> wkatz@xxxxxxxxxx
Phone 303.449-2308
Mobile 303.335-6156
