The first error results from these two models, which are identical
outside of the Aggressor_Only appearances:
[Interconnect Model Set] X9
[Interconnect Model] JJJ | A1 Victim
File_IBIS-ISS dummy.iss aaa
Number_of_terminals = 8
1 Pin_I/O pin_name A1
2 Pad_I/O pin_name A1
3 Pin_I/O pin_name A2
4 Pad_I/O pin_name A2 Aggressor_Only
5 Pin_I/O pin_name A3
6 Pad_I/O pin_name A3 Aggressor_Only
7 Pin_I/O pin_name A4
8 Pad_I/O pin_name A4 Aggressor_Only
[End Interconnect Model]
[Interconnect Model] KKK | A2 Victim
File_IBIS-ISS dummy.iss aaa
Number_of_terminals = 8
1 Pin_I/O pin_name A1
2 Pad_I/O pin_name A1 Aggressor_Only
3 Pin_I/O pin_name A2
4 Pad_I/O pin_name A2
5 Pin_I/O pin_name A3
6 Pad_I/O pin_name A3 Aggressor_Only
7 Pin_I/O pin_name A4
8 Pad_I/O pin_name A4 Aggressor_Only
[End Interconnect Model]
If you don't resolve the fact that terminal 2 in the second model
confers its aggressor-only status onto terminal 1, then yes it appears
the two terminal 1s conflict.
We caused confusion in two steps:
1. Not requiring Aggressor_Only on every terminal of a path as long as
there is one.
2. Not using language that distinguishes the appearance of
Aggressor_Only on a terminal line from the aggressor-only state that
it confers to the path that both terminals are on.
But I assume for now this is easily fixed; the aggressor-only status
needs to be resolved for all terminals using logical propagation before
making the checks.
Mike
On 8/19/2019 12:22 PM, Bob Ross wrote:
All,
A test case is attached to illustrate these contradictory rules under [Interconnect Model Group]
Page 32:
Identifiers associated with these Termimal_type *_I/Os are pin_name entries. In addition, some *_I/O terminals may have the optional Aggressor_Only column. If any *_I/O pin is marked as Aggressor_Only, then any *_I/O pin with the same pin_name entry shall be considered as an aggressor, and not a victim. Any *_I/O Terminal_type without the Aggressor_Only column may be considered as an aggressor or a victim.
Page 33:
oNo I/O pin_name in a component may appear as a Pin_I/O terminal without the Aggressor_Only column in more than one Interconnect Model in the Interconnect Model Group.
oNo I/O pin_name in a component may appear as a Buffer_I/O terminal without the Aggressor_Only column in more than one Interconnect Model in the Interconnect Model Group.
---
The test case currently generates 32 Errors
16 Errors (these can be supressed and are contrary to the page 32 rule)
E6036 - [Interconnect Model Set] X9 [Interconnect Model] QQQ: Terminal 1 and Terminal 2 both don't have Aggressor_Only defined though the pin_name is same
16 Errors (only the Pad_I/O is marked Aggresssor_Only, but the [Interconnect Model]s violate the rules on page 33)
E5908 - [Component] Fake1 [Interconnect Model Group] Y9: Pin_I/O Pin A1 appears in a terminal without the Aggressor_Only attribute in more than one contained model in the group
E5908 - [Component] Fake1 [Interconnect Model Group] Y9: Buffer_I/O Pin A1 appears in a terminal without the Aggressor_Only attribute in more than one contained model in the group
----
Two possible solutions to make the test case legal:
1.Contrary to the rule on page 32, require marking Aggressor_Only on two [Interconnect Model] interfaces with the same *_/I/O pin_name, OR
2.Interpret the rules on page 33 to mean “without the Aggressor_Only column (whether marked or unmarked)”
The Specification needs to be fixed. We can bring this up at the meetings.
Bob
--
Bob Ross
Teraspeed Labs
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