[ibis-macro] A_to_D and D_to_A
- From: Gregory R Edlund <gedlund@xxxxxxxxxx>
- To: ibis-macro-bounce@xxxxxxxxxxxxx, ibis-macro@xxxxxxxxxxxxx
- Date: Thu, 12 Apr 2012 11:49:17 -0500
In reading through the BIRDs that have been tabled, I found myself going
back to the original [External_Model] syntax from IBIS 4.2. I'm having a
hard time wrapping my head around the whole "analog-to-digital" thing. Can
anybody give me a simple example of when you might need a model like the
one described in the 4.2?
| +==================================================+
| | "Model Unit" +--------+|
| | +--------+ | ||
| D_receive --|-<| A_to_D |--<(analog receive ports)--<| ||--
A_puref
| | +--------+ | A pure ||
| | | analog ||--
A_pdref
| | +--------+ | I/O ||
| D_drive --|->| D_to_A |-->(analog drive ports) -->| buffer ||--
A_signal
| | +--------+ | model ||
| | | ||--
A_pcref
| | +--------+ | ||
| D_enable --|->| D_to_A |-->(analog enable ports) -->| ||--
A_gcref
| | +--------+ | ||
| | +--------+|
| +==================================================+
| Model Unit consists of SPICE, VHDL-A(MS), Verilog-A(MS) code plus
| A_to_D and D_TO_A converters
| (references for D_to_A and A_to_D converters not shown)
|
| Figure 6: An analog-only Model Unit, using an I/O buffer as an example
Greg Edlund
Senior Engineer
Signal Integrity and System Timing
IBM Systems & Technology Group
3605 Hwy. 52 N Bldg 050-3
Rochester, MN 55901
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