Greg, [External Model] or [External Circuit] basically instantiates a VHDL-AMS, Verilog-AMS, Verilog-A, or SPICE model. The last two can only have analog terminals (ports) on their interface. The first tow may have analog or digital terminals (ports), and it is up to the model maker to decide who they connect their model to the outside world. In IBIS, we assume that the EDA tool's stimulus is purely digital (whether this is true in reality or not). So the stimulus for a driver, D_drive and the enable signal, D_enable are considered a logic '1' or '0', not a voltage. In order to drive the terminals of a purely analog model, you need to have a D_to_A converter. The drawing you are asking about tries to illustrate how these converters are inserted (automatically) by the EDA tool between its stimulus and the analog terminals of the model. Does this answer your question? Thanks, Arpad ================================================================ From: ibis-macro-bounce@xxxxxxxxxxxxx [mailto:ibis-macro-bounce@xxxxxxxxxxxxx] On Behalf Of Gregory R Edlund Sent: Thursday, April 12, 2012 11:49 AM To: ibis-macro-bounce@xxxxxxxxxxxxx; ibis-macro@xxxxxxxxxxxxx Subject: [ibis-macro] A_to_D and D_to_A In reading through the BIRDs that have been tabled, I found myself going back to the original [External_Model] syntax from IBIS 4.2. I'm having a hard time wrapping my head around the whole "analog-to-digital" thing. Can anybody give me a simple example of when you might need a model like the one described in the 4.2? | +==================================================+ | | "Model Unit" +--------+| | | +--------+ | || | D_receive --|-<| A_to_D |--<(analog receive ports)--<| ||-- A_puref | | +--------+ | A pure || | | | analog ||-- A_pdref | | +--------+ | I/O || | D_drive --|->| D_to_A |-->(analog drive ports) -->| buffer ||-- A_signal | | +--------+ | model || | | | ||-- A_pcref | | +--------+ | || | D_enable --|->| D_to_A |-->(analog enable ports) -->| ||-- A_gcref | | +--------+ | || | | +--------+| | +==================================================+ | Model Unit consists of SPICE, VHDL-A(MS), Verilog-A(MS) code plus | A_to_D and D_TO_A converters | (references for D_to_A and A_to_D converters not shown) | | Figure 6: An analog-only Model Unit, using an I/O buffer as an example Greg Edlund Senior Engineer Signal Integrity and System Timing IBM Systems & Technology Group 3605 Hwy. 52 N Bldg 050-3 Rochester, MN 55901