[ibis-macro] Re: Comment on the minutes of the last meeting
- From: "Todd Westerhoff" <twesterh@xxxxxxxxxx>
- To: <arpad.muranyi@xxxxxxxxx>, <ibis-macro@xxxxxxxxxxxxx>
- Date: Mon, 20 Nov 2006 15:50:19 -0500
I stand corrected.
Todd ;-)
Todd Westerhoff
VP, Software Products
SiSoft
6 Clock Tower Place, Suite 250
Maynard, MA 01754
(978) 461-0449 x24
twesterh@xxxxxxxxxx
www.sisoft.com
-----Original Message-----
From: ibis-macro-bounce@xxxxxxxxxxxxx
[mailto:ibis-macro-bounce@xxxxxxxxxxxxx] On Behalf Of Muranyi, Arpad
Sent: Monday, November 20, 2006 3:49 PM
To: ibis-macro@xxxxxxxxxxxxx
Subject: [ibis-macro] Comment on the minutes of the last meeting
As I was reading the minutes of the last IBIS-ATM teleconference, I
noticed this line:
"Todd: Cadence prefers Verilog, Mentor prefers VHDL, others can't do both at
all."
I need to disagree, Todd. The tool from Dolphin, SMASH can cosimulate
VHDL-AMS, Verilog-AMS and SPICE (plus their own language called ABCD, I
believe), they can even be mixed within the same file...
Arpad
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