Walter
For the purposes of the datasheet the setup conditions were with Vcc = 0V. But
Vcc is not always GND as seen in the test setup in the datasheet. The
specified voltages are with respect to Vcc, not GND. The internal working of
an ECL buffer show you that Vcc is the rail at which specifications are
referenced.
Look at FIGURE 1. Vcc = 2V, Vee = -2.5V
One page 4 FIGURE 2, the input voltage is specified between +0.31 to +1.05V.
That would not work if the part was specified as Vcc = GND.
If I could find my old Motorola ECL manual I’d loan it to you. This is
addresses very nicely in it. If you look at a part supplied with Vcc = 0V and
Vee = -5.2V the input and output specifications do not change as a function of
Vee (within reason). But if you supply an ECL part with Vcc = 5V and Vee = 0V
then the input and output specifications are a function of Vcc. If you
remember correctly the termination load for ECL is 50 Ohms to Vcc – 2V. So as
Vcc changes from +4.5 to +5.5V, the termination voltage changes from 2.5 to
3.5V (4.5V – 2V = 2.5V -- 5.5V – 2V = 3.5V). The input’s specification
tracks the output levels.
If you look at the schematic for an ECL buffer the output high is determined by
the base current of the output emitter follower times the internal resistor on
the diff pair plus a Vbe drop in the output device. The output low is the IR
drop of the same resistor and the standing current of the diff pair plus base
current and a diode drop from Vcc.
And yes, the people who are making the datasheets today are taking short cuts
as seen in many ECL datasheets these days. These short cuts make it easier for
people, they don’t have to subtract Voutlow from Vcc to get the voltage one
would see on a DMM readout. ECL started in the 1960s and a -5.2V Vee supply
was used. When TTL and them CMOS became popular with positive supplies
Motorola, National, etc. started specifying their ECL parts with a Vee = 0V/Vcc
=+5V supply and called them PECL. That way you could have a mix of ECL and
TTL/CMOS from a single +5V supply. Yes, people were designing mixed systems
with -5.2/+5V supplies and really did not need to do that. But the ECL parts
were specified to work at Vee = -5.2V and nobody wanted to operate the parts
off spec.
And I’ve modeled CMOS like parts that were specified in the datasheet to
operate between 0 and -5V.
I’ve also modeled parts that have +/-12V supplies that had TTL like input
threshold level but no pin tied to GND. And no logic supply pin either. The
only assumption is the two supplies are of equal magnitude. These parts could
have been run between 0 and +2*V or 0 and -2*V.
It is likely that none of these strange setups will ever dominate the market
and your assumption covers most chips designers will encounter but not all.
IBIS was set up assuming there were no tri-state ECL parts either but I’ve seen
many of them.
Tom Dagostino
971-279-5325
<mailto:tom@xxxxxxxxxxxxxxxxx> tom@xxxxxxxxxxxxxxxxx
LogoAddress
From: ibis-macro-bounce@xxxxxxxxxxxxx [mailto:ibis-macro-bounce@xxxxxxxxxxxxx] ;
On Behalf Of Walter Katz
Sent: Monday, February 29, 2016 3:24 PM
To: Tom Dagostino; mlabonte@xxxxxxxxxx
Cc: IBIS-ATM
Subject: [ibis-macro] Re: Determining the reference signal_name of an I/O buffer
Tom,
The data book says VCC is GND which is the reference voltage for all
measurements on the chip.
There is nothing that prevents hooking up a different voltage relative to
chassis ground to this pin, but all measurement for inputs and outputs shall be
relative to this VCC reference voltage.
I assume that VCC will be one of the rail voltages supplied to the device (e.g.
Power Clamp Reference). Then [Power Clamp Reference] would be 0.0V. The EDA
tool can certainly supply any voltage it want to this device.
Walter
From: Tom Dagostino [mailto:tom@xxxxxxxxxxxxxxxxx] ;
Sent: Monday, February 29, 2016 6:10 PM
To: wkatz@xxxxxxxxxx; mlabonte@xxxxxxxxxx
Cc: 'IBIS-ATM' <ibis-macro@xxxxxxxxxxxxx>
Subject: RE: [ibis-macro] Re: Determining the reference signal_name of an I/O
buffer
Walter
Like all ECL like parts the input and output voltages are specified with
respect to Vcc, the most positive supply no matter how the part is hooked to
supplies. This part can be run from -5/0V, 0/+5V or -2.5/+2.0V. They test
this part with a -2.5/+2V setup. The voltages specified in the spec sheet are
for Vcc = 0V.
Tom Dagostino
971-279-5325
<mailto:tom@xxxxxxxxxxxxxxxxx> tom@xxxxxxxxxxxxxxxxx
LogoAddress
From: ibis-macro-bounce@xxxxxxxxxxxxx [mailto:ibis-macro-bounce@xxxxxxxxxxxxx] ;
On Behalf Of Walter Katz
Sent: Monday, February 29, 2016 2:23 PM
To: Tom Dagostino; mlabonte@xxxxxxxxxx
Cc: IBIS-ATM
Subject: [ibis-macro] Re: Determining the reference signal_name of an I/O buffer
Tom,
Thank you for find this part. Can you tel me the IC Vendor and a vendor part
number so that I can look at their data sheet. Since they are measuring
voltages, I would like to know how they indicate what is the reference pin for
the voltages that are being measured.
Walter
From: Tom Dagostino [mailto:tom@xxxxxxxxxxxxxxxxx] ;
Sent: Monday, February 29, 2016 2:48 PM
To: mlabonte@xxxxxxxxxx; wkatz@xxxxxxxxxx
Cc: 'IBIS-ATM' <ibis-macro@xxxxxxxxxxxxx>
Subject: RE: [ibis-macro] Re: Determining the reference signal_name of an I/O
buffer
If you look at ECL chips you will find there is no GND in them. There is a Vee
and a Vcc. One common way of connecting ECL chips is to have Vcc at 2V and Vee
at -3.2 or -1.3V. Enclosed is an example test circuit. There are no pins with
GND in this chip. The input and output voltages are specified as Vcc – Xspec.
I’ve also worked with serial data chips that have magnetic coupling between the
input stage and the output stage. The output stage is meant to float with
respect to the input. Think about a communications link between two different
buildings where there are two different “grounds” with distinctly different
voltages on them. We cannot state the output high voltage is 3.3V when
measured at the input reference GND. It may be 1,603V, or -2,163.4V. Yes, you
can tie the two grounds together and you can have local “grounds”. But within
the confines of an IBIS model GND1 is not GND2. See ADM2486.
And while we are at it there is a whole class of other serial communication
chips that generate their own voltages internally. The parts are power by a
3.3V supply but the output has to swing from say -5V to +5V. There are voltage
doublers in these chips with flying capacitors. There is no hard fixed supply.
The output impedance of these supplies is not very low.
And there is another class of chips that have internal LDOs built into them.
And I’m seeing more and more of these. The pullup and Powerclamp references
are not power supplies on the board. For example in one recent part there was
a single 3.3V supply to the chip. Some of the output and input buffers worked
off the 3.3V supply. But other worked off an internally generated 1.8V supply.
And one chip recently had 3.3V and 1.8V supplies. One set of output buffers
could work directly off the 3.3V supply or they could be switched to an
internally generated 2.1V supply.
One of the assumptions all SI simulators make is the supply can both sink and
source current. In a large board this works fine for SI purposes because there
are enough current sinks on the board that any part whose power clamp is
supplying current to the supply has a place for this current to flow. But with
these local LDO features any overshoot causing a Powerclamp to conduct will
upset the local supply. There is usually a pin in these LDO based chips to
bypass the supply, but not always.
Regards,
Tom Dagostino
971-279-5325
<mailto:tom@xxxxxxxxxxxxxxxxx> tom@xxxxxxxxxxxxxxxxx
LogoAddress
From: ibis-macro-bounce@xxxxxxxxxxxxx [mailto:ibis-macro-bounce@xxxxxxxxxxxxx] ;
On Behalf Of Mike LaBonte
Sent: Sunday, February 28, 2016 8:36 PM
To: wkatz@xxxxxxxxxx
Cc: IBIS-ATM
Subject: [ibis-macro] Re: Determining the reference signal_name of an I/O buffer
I think we need to be clear at all times whether it is sufficient to identify a
reference signal_name or if an exact pin must be identified. The first sentence
of this goes both ways. One question is whether the parasitics of the
interconnect shorting the pins associated with one signal together are small
enough to warrant claiming that it wouldn't matter which of those pins were
used as a measurement reference node. I'm not so sure, particularly if package
parasitics are in play.
A potential conflict might come up with BIRD 161.1 Supporting Incomplete and
Buffer-only [Component] Descriptions <http://ibis.org/birds/bird161.1.docx> .
It has not yet passed, but it proposes allowing the first column of [Pin] to
give pad names instead of pin names. At least in that case we would know pin
parasitics were absent. But it allows says that a [Pin] section could have just
one pin.
IBIS has always supported producing models from hardware measurement, but it is
not certain that IBIS requires models to be expressed as though hardware had
been measured when it wasn't. A quick search tells me I have 169 IBIS files on
hand that do not contain the word "GND".
Mike
_____
From: "Walter Katz" <wkatz@xxxxxxxxxx>
To: "IBIS-ATM" <ibis-macro@xxxxxxxxxxxxx>
Sent: Sunday, February 28, 2016 12:08:20 PM
Subject: [ibis-macro] Determining the reference signal_name of an I/O buffer
All,
Continuing this thought, since IBIS is a component measurement based system,
and since measurement are made at the pin of a component, and since every
measurement at an I/O pin is made between that pin and some nearby reference
pin, then all we need to do is define a method of determining the reference
signal_name for every I/O pin. The following algorithm should work for all
known existing IBIS models:
1. [Pin Mapping] tells the bus_label on each of the buffer rail terminals.
2. These bus_labels define the signal_name on each of the rail terminals.
3. If just one signal_name is on a Pin with Model_name GND, and the
values of the Pullup Reference, Power Clamp Reference, Ground Clamp Reference,
Pulldown Reference assigned that has that signal_name has a value of 0.0V in
the [Model], then a pin of that signal_name near the I/O pin is the reference
for the measurements at the I/O pin. Similarly, the I/O buffer rail terminal
with the reference signal_name at the I/O buffer is the reference node for
measurements at the I/O buffer. Similarly, the supply pads at the die/package
boundary near the I/O die pad are the reference for measurements at the I/O die
pad.
If this algorithm does not work for an I/O buffer (and I claim such a case does
not exist) then we can enhance IBIS by adding an option [I/O Reference] section
that has two columns. The first column is the Pin_name of an I/O buffer, and
the second column is the signal_name of the reference for all measurements at
the I/O buffer.
Walter
From: Walter Katz [mailto:wkatz@xxxxxxxxxx] ;
Sent: Saturday, February 27, 2016 8:58 PM
To: IBIS-ATM <ibis-macro@xxxxxxxxxxxxx>
Subject: One of the rail voltages of every IBIS buffer is a GND signal_name and
a reference node.
All,
I have looked at the data sheets for parts with RS232, ECL, PECL and MECL
buffers, and every one of them has one of the rail voltages connected to a
Ground (GND) data book name (signal_name).
Although the IBIS standard does allow the user to associate all of the rail
voltages with bus_labels on POWER pins, such a buffer is an unnatural act.
If we state that it is a given that every buffer has a Ground rail connection,
then we can state that every buffer has a well-defined reference node for every
other terminal measurement at the buffer.
I challenge anyone on this committee to find a part with an I/O buffer that has
no rail terminals that are Ground.
Walter
Walter Katz
<mailto:wkatz@xxxxxxxxxx> wkatz@xxxxxxxxxx
Phone 303.449-2308
Mobile 303.335-6156