All,
After the meeting I added a new [Interconnect Model Group] sub-parameter
"Group_type", with a list of allowed values and rules associated with each
type. I think this addition covers all of the additional functionality
that Bob described in his presentation.
Walter
Walter Katz
<mailto:wkatz@xxxxxxxxxx> wkatz@xxxxxxxxxx
978.461-0449 x 133
Mobile 303.335-6156
From: Walter Katz [mailto:wkatz@xxxxxxxxxx] ;
Sent: Tuesday, November 21, 2017 9:47 AM
To: ibis-interconn@xxxxxxxxxxxxx
Subject: FW: Updated Interconnect Model Group rules, including change to
[Interconnect Model Set]
This was sent from my Gmail account, resending from my SiSoft account.
All,
Replace the following paragraph:
Model makers are recommended to ensure that each Interconnect Model Set
contains a complete description, through Interconnect Models, needed for
the path connecting the I/O buffers of interest to their associated pins,
and for connecting all rails related to these I/O buffers. This
simplifies choices to be made by the user or automatically by the EDA
tool. It also assures that the full electrical structure that is
simulated matches what the model provider intends. Some EDA tools may
support selecting several Interconnect Model Sets at once to form a
complete path, but this requires additional user interaction and may risk
generating less-accurate simulation data due to duplicate or missing
content.
With
An [Interconnect Model Set] contains a list of [Interconnect Model]s that
have a logical association such as:
* All models in a bus (e.g.. DDR4, or PCIeG3)
* PDN Network
* All I/O models between Pad and Pin
* All I/O models between Buffer and Pad
* All uncoupled models
* All coupled models
Change [Interconnect Model Set Group] to [Interconnect Model Group] Done
And add the following paragraph to the Interconnect Model Group section
Add a sub-parameter Group_type with the following allowed values
Pin_to_Pad
Assumes no on-die interconnect models
Pin_to_Buffer
May have Pin to Pad models without Pad to Buffer models on some pin_name
Buffer_to_Pad
(use legacy package models)
Bare_die
(Buffer_to_Pad - no package model)
"Pin" Terminals are not allowed in any model in Bare_die groups
It is the responsibility of the model maker to create Interconnect Model
Groups that contain a list of Interconnect Model Sets that form a list of
Interconnect Models that will satisfy the interconnect modeling
requirements for simulating a group of I/O and or Rail connections. The
following rules shall apply to the combined list of models in all of the
Sets in each Group.
The following rules apply to non-aggressor (victim) I/O Pin_name
terminals:
Errors
If there is a Pin to Buffer model, then
Error if there is a Pin to Pad model or a Pad to Buffer model.
Error if two (or more) models have a buffer terminal with the same
Pin_name
Error if two (or more) models have a pad terminal with the same Pin_name
Error if two (or more) models have a pin terminal with the same Pin_name
If there is a pin to pad model and no pad to buffer model, the pad and
buffer shall be shorted.
If there is a pad to buffer model and no pin to pad model.
If Group_type is Bare_die
No Package Model
Else
Use legacy package model.
Endif
The following rules apply to aggressor and non-aggressor I/O Pin_name
terminals:
Warnings
If there is a Pin to Buffer model, then
Warning if there is a Pin to Pad model or a Pad to Buffer model.
Warning if two (or more) models have a buffer terminal with the same
Pin_name
Warning if two (or more) models have a pad terminal with the same Pin_name
Warning if two (or more) models have a pin terminal with the same Pin_name
If there is a pin to pad model and no pad to buffer model, the pad and
buffer shall be shorted.
If there is a pad to buffer model and no pin to pad model.
If Group_type is Bare_die
No Package Model
Else
Use legacy package model.
Endif
For models with rail voltages:
If a rail signal name is only on pin terminals, or only on pad terminals
or only on buffer terminals, then these terminals are used to define
references for the interconnect in the model
Ignore the following rail voltage terminal rules on models that a rail
signal name is only on pins, or only on pads or only on buffers.
It is an error if two interconnect models have a connection to the same
buffer rail terminal.
It is an error if two interconnect models have a connection to the same
pin rail terminal.
Walter
