Time: Tuesday, August 28, 2018 at Noon US Pacific Time
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WebEx:
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https://sisoft.webex.com/sisoft/j.php?MTID=m1775c35b7d9a55735fbb2c67876222ba
Meeting Number: 735 161 627
Meeting Password: IBIS
Audio:
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Agenda
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1) Opens
2) Roll call
3) Review of ARs:
Arpad: Send the straw poll email to the ATM
- done
Randy: Investigate if/why/how a clock waveform input might be used
- in progress
Michael M.: Investigate if/why/how a clock waveform input might be used
- in progress
Any other AR-s?
4) Call for any IBIS related patent disclosures
5) Approval of minutes
6) Thoughts on what Micron would like to see for single-ended
AMI changes (Justin)
- presentation
- discussion
7) IBIS-AMI improvements discussion (All)
- strawman poll on topics we may want to write BIRDs for (Bob)
Walter's list from last week:
Single Ended:
Vref/Vcent/VrefDQ/DC_Offset
Moving Vref
Rise/Fall Time asymmetry
Knowing DC Offset (singled ended signaling) in AMI Init and AMI GetWave
How to generate a Waveform into Rx AMI GetWave
Mix of single ended and differential signals
Clock Forwarding
single ended filter needs different algorithms
- EQ effecting Vref
DQ Nibbles (Component Models)
Training
Controller Tx trains the Rx and itself
Controller Rx trains itself, DDR5 has not Tx Equalization
There may be other busses where this is not true
Repeater Redriver Flow:
Adding additional Impulse Response Outputs to Tx AMI_Init and Rx AMI_Init
Power Aware SSO effects on AMI Modeling
Note:
One can add AMI Reserved Parameter
One can change the DLL function call / signatures
One can change the # of Impulse Responses in Impulse Matrix
SiSoft's must have list for DDR4/DDR5
1. DC Offset
2. Flow alternatives for generating IR input to Tx AMI_Init
3. Flow alternatives for generating Waveforms for Rx AMI_GetWave
Original topic list:
a) clock forwarding
b) moving Vref
c) rise/fall asymmetry
- gets worse at higher data rate(?)
- can be handled by EDA tool without changing the DLL footprint
("meld" two edges into one for the DLL)
d) single ended filter needs different algorithms
- EQ effecting Vref
e) loss of information when using difference signals only
f) power aware simulation (SSO effects)
8) Input thresholds/measurement target information and (Walter)
eye diagram specification (including BER)
- any feedback/comment from EDA vendors?
9) Complex C_comp modeling (Randy)
- discussion?
10) Motion to adjourn?
Topic bin list:
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- Removing the single-ended input threshold requirements for
differential buffers
- Removing the single-ended characterization load requirements for
differential buffers
- Guidance for power-aware vs. AMI models - do we have rules for
how a power-aware (and therefore potentially non-LTI) buffer
analog data set should be used with IBIS-AMI algorithmic data?
- Fix all the referencing problems in the current specification
(after Randy's C_comp proposal and BIRD189 are done)
- IBIS-AMI Post Simulation Processing (FEC) (Mike L.)
Tabled topics:
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11) New BIRDs from Editorial Task Group? (Bob/Radek)
a) Specify buffer reference terminals for pins ([Pin Reference])
b) Simulation (aka DIA) vs. DUT (depends on #a)
c) C_comp and package reference in simulation clarifications
(depends on #a)
d) Make changes to the [Receiver Threshold], once a) and b) are
resolved
12) 166.4 Resolving problems with Redriver Init Flow (Walter)
13) BIRD190 (Ambrish)
14) Fangyi's Redriver flow BIRD draft (Fangyi)
- add equations
- consider rewriting the AMI "front end" in the spec (flows)
(when this proposal is added to the spec)
15) How to handle missing min/max data? (Arpad)
- what should be the governing rule for synchronizing
typ/min/max data?
Pending BIRDs awaiting discussion:
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166.4 Resolving problems with Redriver Init Flow
181.1 I/V Table Clarifications
190 Clarification for Redriver Flow
195.1 Enabling [Rgnd] and [Rpower] Keywords for Algorithmic Input Models
TBD New proposal for Redriver Flow (may replace BIRD166)
TBD C_comp modeling with IBIS-ISS
Thanks,
Arpad
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