[ibis-macro] Re: Pre/de emphasis buffer model
- From: "Muranyi, Arpad" <arpad.muranyi@xxxxxxxxx>
- To: <ibis-macro@xxxxxxxxxxxxx>
- Date: Mon, 16 Jan 2006 13:57:12 -0800
Paul,
I am putting my responses after your questions.
Let me know if you have any more questions.
Arpad
================================================
-----Original Message-----
From: ibis-macro-bounce@xxxxxxxxxxxxx [mailto:ibis-macro-bounce@xxxxxxxxxxxxx]
On Behalf Of Paul Fernando
Sent: Sunday, January 15, 2006 3:47 PM
To: Muranyi, Arpad
Cc: ibis-macro@xxxxxxxxxxxxx
Subject: [ibis-macro] Pre/de emphasis buffer model
Although I initially meant this email for Arpad, I realized that it made more
sense to
mail it to the entire group. Please feel free to comment. Perhaps we could
discuss some
of it during this weeks meeting.
Hi Arpad,
I got the attached file from the sisoft ibis-macro site and simulated it
successfully-
BTW, IT is still checking if we (NCSU) have SP1 (& the newer patch) for hspice
installed.
Could you please check my reasoning in understanding the flow. Perhaps you
could add
comments at the ends of the paragraphs that would aid my understanding.
I can see that the 'PreDeMacro' model instantiates the 'IBIS_IO' model in the
macro
library. This model approximates the IV & VT curves only based on 4 points. In
the
example, the primary & tap1 drivers have the same IV & VT data. So, if I was to
actually
model a 2-tap preemphasis buffer, I would get the IV & VT tables for each tap
and plug
these points in this section (& I would need 2 library models, IBIS_IO_PRIMARY &
IBIS_IO_TAP1). Alternatively, in its updated final state, I'm assuming, we'll
only have
IBIS_IO in the library and the user can select external files that contain the
IV & VT
curves for each tap. Is my understanding correct? Have we reached this point
yet?
AM: Close. You can select the IV and Vt curves the way you suggested,
but it could also be done with the current scaling mechanism (next question).
Yes, the library will contain only one of each buffer type. The IV and Vt
tables can be passed into that model as parameter(s) from the calling statement
in the template (netlist). So no duplication is necessary.
Why are 8 'IBIS_CCCS's instantiated? Their net result seems to be nothing since
they
source and sink equal current. If they are used to implement some kind of
scaling, whats
the purpose?
AM: You can usually use current sources as shown in that
example to scale the IV curve(s) in the model. Since the
MAIN and the DE-EMPH buffers are usually identical circuits
on the same technology, one can model them with the same IV
curve with a scaling coefficient. This method may make it
easier to implement an FIR filter driven buffer in which the
filter coefficients change on the fly, real time. You wouldn't
be able to do that if you had to change file name references
to switch from one IV curve to another...
I managed to easily create a 3-tap model and I could see the 3-tap response in
the
awaves, but, like I mentioned earlier, this example used the same IV & VT
points to
describe all the taps, so it is not realistic.
AM: Good. The example I made with 4-point IV and Vt
curves using 5V supplies is not realistic either... to
say the least, it was just an illustration to show how
you would go about connecting the library elements, etc...
if you had the correct models.
---------------------
When the group mentioned 'creating new templates' did you mean creating basic
files
(like PreDeMacro.va) for DDR, LVDS, multistage buffers etc? Or was it templates
as part
of the macro library file (like IBIS_IO)?
AM: The former.
Also, in this example, the Verilog-A file is directly run in hspice. My idea of
the
final product would be, the IBIS file is instanced in hspice using the b-elem
and that
ibis file's model would (only?) have an [external circuit] reference to the
verilog-A
file. Is this correct?
AM: HSPICE doesn't support [External Model] or [External Circuit]
in the B-element as far as I know. The B-element is only for legacy
IBIS stuff. You can build a macro model two ways:
1) Using the B-element and some stuff around it you can write a
template for what you want (can), using the HSPICE netlist language, or
2) Using the Verilog-A(MS) library's IBIS_IO and some other stuff
around it from the library, you can write a template for what you want
(can), using the Verilog-A(MS) language
For other tools, the IBIS file would reference the Verilog-A(MS)
template as an [External Model] or [External Circuit] and which is
used as an advanced buffer of some sort. The underlying library is
not known to the tool, from the IBIS point of view, that is taken
care of by the Verilog-A(MS) netlist inside the template.
If this tool doesn't know the Verilog-A(MS) language, it will
recognize that the template is using the library elements, and it
will try to substitute for those elements with its own SPICE primitives.
---------------------
As far as the proposed IBIS to Verilog-A converter goes:
1. What is the purpose here?
AM: To extract a model's IV and Vt tables and put them into
a Verilog-A(MS) syntax so that the instantiation in the template
could refer to a file contained the data and use it. Remember,
we couldn't write a file parsing routine in the library to open
the IBIS file and find the model and read its data, like HSPICE
does it with the B-element. Your script will need to do that.
2. Taking the 2-tap preemphasis buffer as an example, could you explain what it
means to
convert its IBIS file to a Verilog-A instance, given that the only initial file
available is its hspice netlist?
AM: I need to correct the question a little. "...given the
only initial file available is A VERILOG-A(MS) TEMPLATE NETLIST
AND THE MACRO LIBRARY". Answer: If the template uses IV and Vt
data tables which are coming from a [Model] statement in an IBIS
file, the conversion will mean the following: Open the IBIS
file, find the [Model] keyword whose data is needed, and then
find the various keywords and subparameters whose data is used
in the Verilog-A(MS) model. Extract all this data and format
it into a Verilog-A(MS) format so that the instantiation in the
template could refer to this file as a Verilog macro text and
use it in the instantiation line as parameters to the library
element (IBIS_IO, etc).
Regards,
Paul Fernando
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