[ibis-macro] Re: Pre/de emphasis buffer model
- From: "Muranyi, Arpad" <arpad.muranyi@xxxxxxxxx>
- To: <ibis-macro@xxxxxxxxxxxxx>
- Date: Tue, 17 Jan 2006 08:39:17 -0800
Paul,
I am glad that the picture is clearing up in
your mind... Please find the other .DAT files
in the attachment. I tested four conditions,
1) No ODT
2) ODT to Vcc
3) ODT to GND
4) ODT to both Vcc and GND
Regarding how to find the scaling coefficients,
you can also estimate them by comparing the IV
curves (if that's what you have) for the various
stages, and then fins a scaling coefficient from
that. By the way, using L and W for this may not
work because the output current depends mostly
on the current source's current, not the L and W
of the switching transistors, and the current of
the current source depends greatly on the bias
voltage on its gate, and not so much on the L and
W of the transistor.
Yes, the data in these .DAT files should pretty
much be all the parameters in the module.
Arpad
==================================================
-----Original Message-----
From: Paul Fernando [mailto:prfernan@xxxxxxxx]
Sent: Monday, January 16, 2006 4:09 PM
To: Muranyi, Arpad
Cc: ibis-macro@xxxxxxxxxxxxx
Subject: Re: [ibis-macro] Re: Pre/de emphasis buffer model
Arpad,
Thanks for the clarifications. My understanding has improved considerably.
Now I understand how the CCCS's scale the tap currents; although it does
require the
model writer to know the tap coeffs, which might be a down side since he'll
need a high
level model of the design to get those values... unless he approximates it
based on the
W/L ratios.
I can also see how the following lines read the IV & VT tables as part of the
instantiation. The problem is that the zip file I got doesn't have
"IV_data_no_ODT.dat"
& "VT_data_no_ODT.dat". Could you please send me these files or something
similar?
//-----------------------------------------------------------------------------
// These lines show how to pass IV and Vt tables into the IBIS_IO model
//-----------------------------------------------------------------------------
//`include "IV_data_no_ODT.dat"
//`include "VT_data_no_ODT.dat"
// IBIS_IO #(`IV_data, `VT_data) PosM (PUref, PDref, IOp, InD, EnD,
RcvPM,
PCref, GCref);
// IBIS_IO #(`IV_data, `VT_data) NegM (PUref, PDref, IOn, InNM, EnD,
RcvNM,
PCref, GCref);
// IBIS_IO #(`IV_data, `VT_data) PosB (PUrefPB, PDrefPB, IOp, InPB, EnD,
RcvPB,
PCrefPB, GCrefPB);
// IBIS_IO #(`IV_data, `VT_data) NegB (PUrefNB, PDrefNB, IOn, InNB, EnD,
RcvNB,
PCrefNB, GCrefNB);
//// PUref, PDref, IO, In, En,
Rcv,
PCref, GCref
//-----------------------------------------------------------------------------
As for the IBIS to Verilog-A converter, I understand its purpose now. I guess a
starting
point would be to create a script that create files like "IV_data_no_ODT.dat" &
"VT_data_no_ODT.dat" (in the above example) using an IBIS model as the input.
So basically, the model writer is expected to model the primary driver in IBIS
and
provide it to the IBIS to Verilog-A converter. Right?
As for data that must be passed as part of the instantiation process, are they
all the
parameters in the IBIS_IO model? (C_comp, Vinh, Vinl, V_pc_ref, V_pu_ref,
V_pd_ref,
V_gc_ref, IV & VT tables etc.)
Regards,
Paul
Other related posts:
