[ibis-macro] Re: Updates to BIRD 145
- From: "Muranyi, Arpad" <Arpad_Muranyi@xxxxxxxxxx>
- To: "james.zhou@xxxxxxxxxx" <james.zhou@xxxxxxxxxx>, Feras Al-Hawari <feras@xxxxxxxxxxx>, 'IBIS-ATM' <ibis-macro@xxxxxxxxxxxxx>
- Date: Tue, 6 Mar 2012 18:57:30 +0000
James,
I think the mapping rules are pretty well defined in the v5.0
specification and illustrated on pg. 136-138 in the spec.
If you use the name of a [Pin] in Port_map, the assumption
is that this connection is made to a pad on the dies that is
connected to the pin with a 1-to-1 package path. If you
use a declared die node name (which can also serve as an
on-die pad name), you are making a connection to a declared
on-die node or die-pad for [External ***] in the Port_map.
BIRD 145 seems to allow the connection between reserved
power and GND ports to on-die nodes (which is new). This
is shown in example 1, using nodes a1, b1, d1, e1 and
a2, b2, d2, e2. In the past, these power and GND reserved
nodes could only be connected (and grouped) via the
[Pin Mapping] keyword to specific "pins", which were
actually on-die pads with an assumed 1-to-1 mapping
between pins and pads. Example 2 of BIRD 145 shows that
you can still use the old way of connecting these power
ports if you don't spell them out in the Port_map.
However, Figure 12 on pg. 136 included a few things which
are actually not supported in the specification yet. For
example, the association between pad_2a and pad_2b and pin 2
or pad_4 and pins 4a and 4b, but even pad_11 and pin 11
cannot be defined with the current package modeling
capabilities in IBIS. This figure was a forward looking
example using the ideas we were working on with the ICM
specification. Unfortunately we never finished these
concepts.
BIRD 145 does not address these non 1-to-1 package modeling
issues. That should be dealt with in a package BIRD, and
I am actually addressing that in BIRD 125.
I hope this answers your questions.
Thanks,
Arpad
==============================================================
From: ibis-macro-bounce@xxxxxxxxxxxxx [mailto:ibis-macro-bounce@xxxxxxxxxxxxx]
On Behalf Of James Zhou
Sent: Monday, March 05, 2012 7:57 PM
To: Feras Al-Hawari; 'IBIS-ATM'
Subject: [ibis-macro] Re: Updates to BIRD 145
Hi Feras,
in BIRD145, example 1:
[Circuit Call] RDL_Interconnect | Instantiates [External Circuit] named
| "RDL_Interconnect"
| mapping port pad/node
Port_map vcc 18 | Port to implicit pad connection
Port_map gnd 12 | Port to implicit pad connection
What are the rules to map pad/node to pins? In this example, the die pads have
the same name as the pin names. However, in a general cases (such as the one
shown in IBIS 5.0 page 136-138,) the die pads and pins have different names.
This applies to both BIRD 145 and IBIS 5.0.
Also when it involves power ground pins, the mapping from die pads to pins are
almost never 1 to 1 and how does IBIS or BIRD 145 address this issue?
Regards,
James Zhou
QLogic Corp.
From: Feras Al-Hawari
[mailto:feras@xxxxxxxxxxx]<mailto:[mailto:feras@xxxxxxxxxxx]>
Sent: Monday, March 05, 2012 2:44 PM
To: James Zhou; 'IBIS-ATM'
Subject: RE: Updates to BIRD 145
Hello James,
Both cases could be handled in a more accurate manner if the simulator
supports BIRD 98 and the I/O model contains the KSSO tables. Based on that, the
simulator would scale the IV curves according to the reference voltage
variations (deviations).
Best regards,
Feras
From: James Zhou
[mailto:james.zhou@xxxxxxxxxx]<mailto:[mailto:james.zhou@xxxxxxxxxx]>
Sent: Monday, March 05, 2012 5:21 PM
To: Feras Al-Hawari; 'IBIS-ATM'
Subject: RE: Updates to BIRD 145
Hi Feras,
I have a couple of questions about this BIRD.
Using the following IBIS keywords and values as an example:
---------------------------------------------------------------------------------------------------
[Voltage Range] 1.5000V 1.4250V 1.5750V
[Pullup Reference] 1.5000V 1.4250V 1.5750V
[Temperature Range] 50.0 120.0 -40.0
[Pulldown]
| Voltage I(typ) I(min) I(max)
-1.50000000E+0 -16.49945000E-3 -12.54515100E-3 -17.87071600E-3
-1.42500000E+0 -17.26897000E-3 -13.59391400E-3 -18.38734400E-3
......
---------------------------------------------------------------------------------------------------
Suppose the user has selected the typical case for simulation, corresponding to
voltage = 1.5000V, temperature = 50.0.
For case a) in your email: if an external circuit is inserted between the
external power supply and A_puref, the actual voltage of A_puref can deviate
from 1.5V. As a result the typical V-I curve (which was obtained for
A_puref=1.5000V) will no longer apply to this simulation. What is the proposed
approach for this situation?
For case b) in your email: This BIRD proposes no changes to how the power
supplies are connected to the model when the power nodes are floating. However,
I'd like to enter this question here anyway for the record: what happens if a
user connected the A_puref to a voltage other than 1.5000V (such as 1.52385V)
and selected the typical V-I curve ? Further, what if the user composes a
power circuit outside of IBIS and connects it to the A_puref pins in the EDA
tool?
This BIRD presents a format to include power distribution circuits in IBIS. At
the same time it should also clearly articulate how this new structure and data
should be simulated when power supply voltages deviate from those prescribed
values in native IBIS V-I curves.
Thanks,
James Zhou
QLogic Corp.
From: ibis-macro-bounce@xxxxxxxxxxxxx<mailto:ibis-macro-bounce@xxxxxxxxxxxxx>
[mailto:ibis-macro-bounce@xxxxxxxxxxxxx]<mailto:[mailto:ibis-macro-bounce@xxxxxxxxxxxxx]>
On Behalf Of Feras Al-Hawari
Sent: Monday, March 05, 2012 1:48 PM
To: 'IBIS-ATM'
Subject: [ibis-macro] Updates to BIRD 145
I have updated BIRD 145 (will be uploaded soon) to explain whose responsible
for delivering power to the reserved voltage reference nodes in examples 1 & 2
. The new changes are preceded by **. The bulk of the changes are as shown
below:
|* The pre-defined voltage reference ports (i.e., A_pcref, A_puref,
|* A_pdref, A_gcref) of any [Model] that is called in the circuit
|* can be either: a) manually interconnected by the model developer
to the
|* ports of an [External Circuit] by connecting them to the same
node
|** declared by the [Node Declarations] keyword as shown in example
1 below
|** (i.e., in this case the model developer needs to guarantee that
the
|** [External Circuit] contains the appropriate circuitry to deliver
the
|** required power to each of the voltage reference ports), or b)
automatically
|** interconnected "as usual" by the EDA tool to the corresponding
voltage
|** sources when those ports are left floating as shown in example 2
|** below (i.e., in this case the EDA tool should connect the
reserved
|** voltage reference ports to DC voltage sources with voltage values
|** equal to the corresponding reference voltage values in the
[Model]).
Feras
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