[ibis-macro] Re: EMD Pole-Zero Models (Why voltage controled sources?)
- From: Bob Ross <bob@xxxxxxxxxxxxx>
- To: wkatz@xxxxxxxxxx
- Date: Sun, 29 Jun 2008 19:53:23 -0700
Walter:
Here are some responses to your questions
1. HSPICE and some other SPICEs implement the Laplace and pole-zero
elements as a network function WITHIN controlled sources including
the VCVS (E) and VCCS (G) elements. The documention is hard to
find, but the HSPICE syntax is in the HSPICE Applications Manual:
Exxx n+ n- LAPLACE in+ in- k0 k1 ... kn / b0 b1 ... bm
Gxxx n+ n- LAPLACE in+ in- k0 k1 ... kn / b0 b1 ... bm
Exxx n+ n- POLE in+ in- a {cmpl zeros) / b (cmpl poles}
Gxxx n+ n- POLE in+ in- a {cmpl zeros) / b (cmpl poles}
2. I think of a pole-zero block, not as the single Laplace transfer
element, but as an n-port block such as proposed in some private
Touchstone-like formats and possibly implemented internally
and automatically from n-port table data.
My question:
When you say interconnect block modules of Resistor/Inductor/
Capacitor, do you really mean a low-level SPICE or SPICE-like
syntax within "SPICE" subcircuits for interconnect structures?
That is where K and controlled sources are valuable for many
reasons. While we have not really discussed this, I have been
assuming that we need such low-level capability for EMD. We
could formally add a basic SPICE-syntax subcircuit to the list
below as one of the modules with its internal SPICE-like netlist
used for connecting the R/L/C/K/E/F/G/H ... elements.
Bob
Walter Katz wrote:
> All,
>
>
>
> Based on the following assumptions for an EMD:
>
>
>
> * A module as a netlist of IBIS components and external pins
> * Interconnect models between these IBIS component pins consist of a
> netlist of interconnect blocks
> * Interconnect block models are:
> o Resistors
> o Inductors
> o Capacitors
> o Distributed RLGC models
> o S parameter Models
> o Impulse Response Models
> o Pole-Zero Models
>
>
>
> The purpose of this e-mail is to raise the issue of what is a Pole-Zero
> model and why do we need voltage controlled sources.
>
>
>
> I refer to http://www.ece.uci.edu/docs/hspice/hspice_2001_2-217.html
>
>
>
>
> Understanding Pole/Zero Analysis
>
> In pole/zero analysis, a network is described by its network transfer
> function which, for any linear time-invariant network, can be written in
> the general form:
>
>
>
> In the factorized form, the general function is:
>
>
>
> It seems to me that a Pole-Zero model can either be represented as a set
> of numbers like the polynomial coefficients a0, b0, a1, b1, a2, b2, ..
> or the factorized form a0, b0, z1, p1, z2, p2, ?
>
> Where is the controlled voltage source?
>
> I assume that one can model the pole-zero form into Spice, Verilog, and
> VHDL primitives, and doing so might utilize controlled voltage sources
> and other simulator specific models.
>
> Why it is not sufficient to just have a Pole-Zero model (either with
> polynomial coefficients and/or pole-zero coefficients).
>
> Walter
>
--
Bob Ross
Teraspeed Consulting Group LLC Teraspeed Labs
121 North River Drive 13610 SW Harness Lane
Narragansett, RI 02882 Beaverton, OR 97008
401-284-1827 503-430-1065
http://www.teraspeed.com 503-246-8048 Direct
bob@xxxxxxxxxxxxx
Teraspeed is a registered service mark of Teraspeed Consulting Group LLC
---------------------------------------------------------------------
IBIS Macro website : http://www.eda.org/pub/ibis/macromodel_wip/
IBIS Macro reflector: //www.freelists.org/list/ibis-macro
To unsubscribe send an email:
To: ibis-macro-request@xxxxxxxxxxxxx
Subject: unsubscribe
Other related posts:
