Paul, I tried the Verilog portion of your script today and found a couple of minor things. 1) When the IBIS file doesn't have something, don't print it out in the .dat file. For example, in a 3-state buffer there are no Vinh and Vinl parameters, yet you printed them in the .dat file with zero values. This may apply to all other parameters, and the VHDL portion too, but I didn't test it. The only exception to this rule would be the voltage reference parameters, which I discussed in an earlier reply. 2) You printed three `define statements in the .dat file. While it can be done that way also, I would prefer just to use one at the beginning. If we have multiple definitions, the netlist will have to use the same number of calls in the parameter passing section, and that will begin to look too busy. The whole point of doing it with this .dat file and macro definition was to reduce the amount of typing on the netlist. 3) Cosmetics: You could put an extra "blank" line between the various IV and Vt tables to make it somewhat easier to read (in case someone needs to look at it with an editor). I didn't see a response from you to the suggestions I made on the voltage reference parameters and the association of the waveforms with r1, r2, f1, f2. Do you think you can implement it? Thanks, Arpad ================================================== --------------------------------------------------------------------- IBIS Macro website: http://www.sisoft.com/ibis-macro IBIS Macro archives: //www.freelists.org/archives/ibis-macro To unsubscribe send an email: To: ibis-macro-request@xxxxxxxxxxxxx Subject: unsubscribe