Paul, I found a few problems. 1) The ordering of r1, r2 and f1, f2 are reversed on the Verilog side (but not on the VHDL side). I am not sure how you are doing this, but I find it strange that one is OK and the other is not. 2) The .Vpc_ref(1.500), \ .Vgc_ref(0), \ .Vpu_ref(1.500), \ .Vpd_ref(0), \ values are not getting extracted correctly. This example got 3.3 instead of 1.5. The IBIS file had: [Voltage Range] 1.500 1.350 1.650 I didn't test this on the VHDL side, it may or may not be OK, please check. I am in a meeting now, but will test some more... Thanks, Arpad ==================================================================== --------------------------------------------------------------------- IBIS Macro website: http://www.sisoft.com/ibis-macro IBIS Macro archives: //www.freelists.org/archives/ibis-macro To unsubscribe send an email: To: ibis-macro-request@xxxxxxxxxxxxx Subject: unsubscribe